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| 型號： | P83CE560EFB |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | NPN Silicon Power Transistor, TO-220F-3SL |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 46/84頁 |
| 文件大小： | 441K |
| 代理商： | P83CE560EFB |
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1997 Aug 01
46
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
15.3
Wake-up from Power-down mode
The Power-down mode of the P8xCE560 can also be
terminated by any one of the three enabled interrupts,
INT0, INT1 or Seconds interrupt.
If there is an interrupt already in service, which has same
or higher priority than the Wake-up interrupt,
Power-down mode will switch over to Idle mode and stay
there until an interrupt of higher priority terminates
Idle mode.
A termination with these interrupts does not affect the
internal Data Memory and does not affect the Special
Function Registers. This gives the possibility to exit
Power-down without changing the port output levels.
To terminate the Power-down mode with an external
interrupt, INT0 or INT1 must be switched to be
level-sensitive and must be enabled. The external interrupt
input signal INT0 or INT1 must be kept LOW till the
oscillator has restarted and stabilized (see Fig.15).
A Seconds interrupt will terminate the Power-down mode
if it is enabled and INT1 is level sensitive. In order to
prevent any interrupt priority problems during Wake-up,
the priority of the desired Wake-up interrupt should be
higher than the priorities of all other enabled interrupt
sources.
The instruction following the one that put the device into
the Power-down mode will be the first one which will be
executed after the interrupt routine has been serviced.
15.4
Status of external pins
Table 69
Status of external pins during Idle and Power-down modes
Note
1.
In Idle mode SCL and SDA can be active as outputs only if SIO1 is enabled; if SIO1 is disabled (S1CON.6/ENS1 = 0)
these pins are in a high-impedance state.
MODE
MEMORY
ALE
PSEN
PWM0/
PWM1
PORT0
PORT1
PORT2
PORT3
PORT4
SCL/ SDA
Idle
internal
external
1
1
0
0
1
1
0
0
1
1
1
1
port data port data port data port data port data operative
(1)
high-Z
port data address
port data port data operative
(1)
port data port data port data port data port data
high-Z
port data port data port data port data
Power-down internal
high-Z
high-Z
external
Fig.15 Wake-up by interrupt.
handbook, full pagewidth
MBH083
oscillator start-up time
interrupts are polled
Idle mode
LCALL
interrupt routine
>
560 ms
Power-down mode
internal timing stopped
32 kHz oscillator stopped
>
10 ms
32 kHz oscillator running
XTAL1, 2 oscillator stopped
C1
INT0
INT1
C1
C1
C2
set external interrupt latch
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