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參數(shù)資料
| 型號(hào)： | P83C270 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)(在NTSC TV中應(yīng)用的具有屏幕顯示和字幕關(guān)閉特點(diǎn)的微控制器) |
| 中文描述： | 微控制器用于NTSC電視的屏幕顯示（OSD）和字幕（CC）的（在NTSC電視中應(yīng)用的具有屏幕顯示和字幕關(guān)閉特點(diǎn)的微控制器） |
| 文件頁數(shù)： | 59/80頁 |
| 文件大?。?/td> | 266K |
| 代理商： | P83C270 |
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1999 Jun 11
59
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
P8xCx70 family
18.9.12
C
ONFIGURATION
R
EGISTER
(CONFR)
The Configuration Register is provided for special purposes and to program the delay between the RGB and FBL output.
Table 99
Configuration Register (address 87FFH)
Table 100
Description of CONFR bits
Table 101
FBL delay adjustment
7
6
5
4
3
2
1
0
CC
PLUS
ADJ
MIN
BIT
SYMBOL
DESCRIPTION
7
CC
Closed Caption mode.
The state of this bit selects the OSD mode or the CC mode.
If CC = 0, then the OSD mode is selected; this is also the default setting. If CC = 1, then
the CC mode is selected. In the CC mode the underline is suppressed during the
display of a serial attribute. The display is then according to the CC specification.
FBL delay select.
These 3 bits define the timing of the FBL signal; see Table 101.
6
5
4
3
2
1
0
PLUS
ADJ
MIN
Reserved, set to logic 0.
These 3 bits are used for test purposes only and should be set to logic 0s for normal
operation.
PLUS
ADJ
MIN
FBL TIMING
0
0
0
1
X
0
0
1
0
X
0
1
0
0
X
FBL switched to video, not active.
FBL active one pixel early to RGB.
FBL synchronous with RGB (typical setting).
FBL active one pixel delayed to RGB.
All other combinations are allowed and will have the effect that the above
settings are functionally ORed, e.g. ‘111’ will result in a 3 pixel wide FBL
pulse when one single pixel is displayed.
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