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參數(shù)資料
| 型號(hào)： | P83C180 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁(yè)數(shù)： | 25/84頁(yè) |
| 文件大?。?/td> | 420K |
| 代理商： | P83C180 |
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1997 Dec 12
25
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
11.4
Status of external pins
If the HSYNC
out
, VSYNC
out
, PATOUT or CLAMP output
is selected (for selection see description in Tables 8
and 18) in Idle or Power-down mode, since sync
separation is still alive in Idle mode, HSYNC
out
,
VSYNC
out
, PATOUT or CLAMP output will be operating
as normal. In Power-down mode: HSYNC
out
, VSYNC
out
,
PATOUT or CLAMP output are pulled HIGH.
In Idle or Power-down mode, if bit DDCE (SFR DFCON)
is set, the function of P1.2 and P1.3 will be switched to
the DDC interface pins SCL1 and SDA1 respectively. In
Idle mode SCL1 and SDA1 can be active only if DDC1
or DDC2 is enabled; otherwise these pins are in the
high-impedance (High-Z) state.
If bit PWME.n (SFR PWME1/PWME2) is set, the
function of P1.7, P2.n, P3.0 and P3.1 will be switched to
the PWM output function. However, in both Idle and
Power-down modes, the output of those PWM pins are
pulled HIGH.
Table 28
Status of external pins during Idle and Power-down modes
MODE
MEMORY
PORT0
TO
PORT 3
HSYNC;
VSYNC;
CLAMP;
PATOUT
SCL
AND
SDA
SCL1
AND
SDA1
PWM0
TO
PWM10
DAC0
TO
DAC3
Idle
Power-down
internal
internal
data
data
operative
HIGH
High-Z
High-Z
operative
High-Z
HIGH
HIGH
unknown
unknown
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