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參數(shù)資料
| 型號： | P82B96T |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual bi-directional bus buffer |
| 中文描述： | 雙雙向總線緩沖器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 217K |
| 代理商： | P82B96T |
Philips Semiconductors
Product data
P82B96
Dual bi-directional bus buffer
2
2004 Mar 26
FEATURES
Bi-directional data transfer of I
2
C-bus signals
Isolates capacitance allowing 400 pF on Sx/Sy side and
4000 pF on Tx/Ty side
Tx/Ty outputs have 60 mA sink capability for driving
low impedance or high capacitive buses
400 kHz operation over at least 20 meters of wire (see AN10148)
Supply voltage range of 2 V to 15 V with I
2
C logic levels on Sx/Sy
side independent of supply voltage
Splits I
2
C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals
for interface with opto-electrical isolators and similar devices that
need uni-directional input and output signal paths.
Low power supply current
ESD protection exceeds 3500 V HBM per JESD22-A114,
250 V DIP package / 400 V SO package MM per JESD22-A115,
and 1000 V CDM per JESD22-C101
Latch-up free (bipolar process with no latching structures)
Packages offered: DIP, SO, and TSSOP
TYPICAL APPLICATIONS
Interface between I
2
C buses operating at different logic levels
(e.g., 5 V and 3 V or 15 V)
Interface between I
2
C and SMB (350
μ
A) bus standard.
Simple conversion of I
2
C SDA or SCL signals to multi-drop
differential bus hardware, e.g., via compatible PCA82C250.
Interfaces with Opto-couplers to provide Opto isolation between
I
2
C-bus nodes up to 400 kHz.
DESCRIPTION
The P82B96 is a bipolar IC that creates a non-latching,
bi-directional, logic interface between the normal I
2
C-bus and a
range of other bus configurations. It can interface I
2
C-bus logic
signals to similar buses having different voltage and current levels.
For example it can interface to the 350
μ
A SMB bus, to 3.3 V logic
devices, and to 15 V levels and/or low impedance lines to improve
noise immunity on longer bus lengths.
It achieves this interface without any restrictions on the normal I
2
C
protocols or clock speed. The IC adds minimal loading to the I
2
C
node, and loadings of the new bus or remote I
2
C nodes are not
transmitted or transformed to the local node. Restrictions on the
number of I
2
C devices in a system, or the physical separation
between them, are virtually eliminated. Transmitting SDA/SCL
signals via balanced transmission lines (twisted pairs) or with
galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals
may be directly connected, without causing latching, to provide an
alternative bi-directional signal line with I
2
C properties.
PIN CONFIGURATIONS
8-pin dual in-line, SO, TSSOP
1
2
3
4
5
6
7
8
Sx
Rx
Tx
GND
Ty
Ry
Sy
V
CC
SU01011
PINNING
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SPECIAL NOTE:
Two or more Sx or Sy I/Os must not be interconnected. The P82B96
design does not support this configuration. Bi-directional I
2
C signals
do not allow any direction control pin so, instead, slightly different
logic low voltage levels are used at Sx/Sy to avoid latching of this
buffer. A “regular I
2
C low” applied at the Rx/Ry of a P82B96 will be
propagated to Sx/Sy as a “buffered low” with a slightly higher
voltage level. If this special “buffered low” is applied to the Sx/Sy of
another P82B96 that second P82B96 will not recognize it as a
“regular I
2
C-bus low” and will not propagate it to its Tx/Ty output.
The Sx/Sy side of P82B96 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example
PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended
for, and compatible with, the normal I
2
C logic voltage levels of I
2
C
master and slave chips—or even Tx/Rx signals of a second P82B96
if required. The Tx/Rx and Ty/Ry I/O pins use the standard I
2
C logic
voltage levels of all I
2
C parts. There are NO restrictions on the
interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s,
for example in a star or multi-point configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to
the line card slave devices. For more details see Application
Note AN255
SYMBOL
PIN
DESCRIPTION
Rx
Sx
2
1
Receive signal
I
2
C-bus (SDA or SCL)
Tx
3
Transmit signal
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P82B96TD | 功能描述:緩沖器和線路驅(qū)動器 I2C BUS BUFFER DUAL RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| P82B96TD,112 | 功能描述:緩沖器和線路驅(qū)動器 I2C BUS BUFFER DUAL RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| P82B96TD,118 | 功能描述:緩沖器和線路驅(qū)動器 DUAL BI-DIRECTIONAL BUS BUFFER RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| P82B96TD,118-CUT TAPE | 制造商:NXP 功能描述:P82B96 Series Dual Non-Latching Bidirectional I2C Bus Buffer - SOIC - 8 |
| P82B96TD/S410,118 | 制造商:NXP Semiconductors 功能描述:Bus Buffer 8-Pin SO T/R 制造商:NXP Semiconductors 功能描述:P82B96TD/SO8/REEL13//S410 - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC BUS BUFFER BIDIR DUAL 8SOIC 制造商:NXP Semiconductors 功能描述:Dual Bidirectional Bus Buffer |
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