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參數(shù)資料
| 型號(hào)： | P80CL31HFT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontrollers with UART |
| 中文描述： | 8-BIT, 8 MHz, MICROCONTROLLER, PDSO40 |
| 封裝： | PLASTIC, SOT-158-1, VSO-40 |
| 文件頁數(shù)： | 9/68頁 |
| 文件大?。?/td> | 305K |
| 代理商： | P80CL31HFT |
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1997 Apr 15
9
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART
P80CL31; P80CL51
7.2
Pin description
Table 1
For more extensive description of the port pins see Chapter 10 “I/O facilities”.
Pin description for DIP40 (SOT190-1), VSO40 (SOT319-2) and QFP44 (SOT307-2) packages
SYMBOL
PIN
DESCRIPTION
DIP40
VSO40
QFP44
P1.0/INT2
P1.1/INT3
P1.2/INT4
P1.3/INT5
P1.4/INT6
P1.5/INT7
P1.6/INT8
P1.7/INT9
RST
1
2
3
4
5
6
7
8
9
40
41
42
43
44
1
2
3
4
Port 1
: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have
logic 1s written to them are pulled HIGH by internal pull-ups, and in this
state can be used as inputs. As inputs, Port 1 pins that are externally
pulled LOW will source current (I
IL
, see Chapter 21) due to the internal
pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads.
Alternative functions:
– INT2 to INT9 are external interrupt inputs.
Reset
: a HIGH level on this pin for two machine cycles while the oscillator
is running resets the device.
Port 3:
8-bit bidirectional I/O port (P3.0 to P3.7).
Same characteristics as Port 1.
Alternative functions:
– RXD/data is the serial port receiver data input (asynchronous) or data
input/output (synchronous)
– TXD/clock is the serial port receiver data output (asynchronous) or
clock output (synchronous)
– INT0 and INT1 are external interrupts 0 and 1
– T0 and T1 are external inputs for timers 0 and 1
– WR is the external Data Memory write strobe
– RD is the external Data Memory read strobe.
Crystal oscillator output
: output of the inverting amplifier of the oscillator.
Left open when external clock is used.
Crystal oscillator input
: input to the inverting amplifier of the oscillator,
also the input for an externally generated clock source.
Ground: circuit ground potential.
Port 2
: 8-bit bidirectional I/O port (P2.0 to P2.7) with internal pull-ups.
Same characteristics as Port 1.
High-order addressing
: Port 2 emits the high-order address byte
(A8 to A15) during accesses to external memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses the strong internal
pull-ups when emitting logic 1s. During accesses to external memory that
use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.
Program Store Enable
. Output read strobe to external Program Memory.
When executing code out of external Program Memory, PSEN is activated
twice each machine cycle. However, during each access to external Data
Memory two PSEN activations are skipped.
P3.0/RXD/data
P3.1/TXD/clock
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
10
11
12
13
14
15
16
17
5
7
8
9
10
11
12
13
XTAL2
18
14
XTAL1
19
15
V
SS
P2.0 to P2.7
A8 to A15
20
16
21 to 28
18 to 25
PSEN
29
26
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