參數(shù)資料
型號： P80C591
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller with CAN controller
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 51/161頁
文件大小： 588K
代理商： P80C591
1999 Aug 19
51
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.17.3 Acceptance Filter Priority Register
For each available Acceptance Filter it could be defined, whether a receive interrupt is forced immediately if a message
passes a certain Acceptance Filter or whether the programmed Receive Interrupt Level should be used for interruption.
This allows to use certain Acceptance Filters for alarm message recognition interrupting the host CPU immediately.
Note, that some bits are implemented only in case of the corresponding acceptance filter bank is implemented.
Not implemented bits are read as “0”.
Table 35
Acceptance Filter Priority Register (ACF Priority) (CAN address 31)
7
6
5
4
3
2
1
0
B4F2PRIO
B4F1PRIO
B3F2PRIO
B3F1PRIO
B2F2PRIO
B2F1PRIO
B1F2PRIO
B1F1PRIO
Table 36
Acceptance Filter Priority Register (ACF Priority)
BIT
SYMBOL
NAME
VALUE
FUNCTION
ACFPRIO.7
B4F2PRIO
Bank 4 Filter 2
Priority
1 (high)
A receive interrupt is generated immediately, if a message
passes Filter 2 within Acceptance Filter Bank 4
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
A receive interrupt is generated immediately, if a message
passes Filter 1 within Acceptance Filter Bank 4
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
A receive interrupt is generated immediately, if a message
passes Filter 2 within Acceptance Filter Bank 3
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
A receive interrupt is generated immediately, if a message
passes Filter 1 within Acceptance Filter Bank 3
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
A receive interrupt is generated immediately, if a message
passes Filter 2 within Acceptance Filter Bank 2
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
A receive interrupt is generated immediately, if a message
passes Filter 1 within Acceptance Filter Bank 2
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
A receive interrupt is generated immediately, if a message
passes Filter 2 within Acceptance Filter Bank 1
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
A receive interrupt is generated immediately, if a message
passes Filter 1 within Acceptance Filter Bank 1
A receive interrupt is generated, if the FIFO level exceeds
the Receive Interrupt Level Register.
0 (low)
ACFPRIO.6
B4F1PRIO
Bank 4 Filter 1
Priority
1 (high)
0 (low)
ACFPRIO.5
B3F2PRIO
Bank 3 Filter 2
Priority
1 (high)
0 (low)
ACFPRIO.4
B3F1PRIO
Bank 3 Filter 1
Priority
1 (high)
0 (low)
ACFPRIO.3
B2F2PRIO
Bank 2Filter 2
Priority
1 (high)
0 (low)
ACFPRIO.2
B2F1PRIO
Bank 2 Filter 1
Priority
1 (high)
0 (low)
ACFPRIO.1
B1F2PRIO
Bank 1 Filter 2
Priority
1 (high)
0 (low)
ACFPRIO.0
B1F1PRIO
Bank 1 Filter 1
Priority
1 (high)
0 (low)
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