參數(shù)資料
型號: P80C32X2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 46/62頁
文件大?。?/td> 0K
描述: IC 80C51 MCU 256 ROMLESS 44PLCC
產品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 26
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,UART/USART
外圍設備: POR
輸入/輸出數(shù): 32
程序存儲器類型: ROMless
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
其它名稱: 568-7899-5
568-7899-5-ND
568-8350-5
935269608512
P80C32X2FA
P80C32X2FA,512-ND
P80C32X2FA-ND
Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
50
Table 9. EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/VPP
P2.7
P2.6
P3.7
P3.6
P3.3
Read signature
1
0
1
0
X
Program code data
1
0
0*
VPP
1
0
1
X
Verify code data
1
0
1
0
1
X
Pgm encryption table
1
0
0*
VPP
1
0
1
0
X
Pgm security bit 1
1
0
0*
VPP
1
X
Pgm security bit 2
1
0
0*
VPP
1
0
X
Pgm security bit 3
1
0
0*
VPP
0
1
0
1
X
Program to 6-clock mode
1
0
0*
VPP
0
1
0
Verify 6-clock4
1
0
1
e
0
1
Verify security bits5
1
0
1
e
0
1
0
X
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VPP = 12.75 V ±0.25 V.
3. VCC = 5 V±10% during programming and verification.
4. Bit is output on P0.4 (1 = 12x, 0 = 6x).
5. Security bit one is output on P0.7.
Security bit two is output on P0.6.
Security bit three is output on P0.3.
*
ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while VPP is held at
12.75 V. Each programming pulse is low for 100
s (±10 s) and high for a minimum of 10 s.
Table 10. Program Security Bits for EPROM Devices
PROGRAM LOCK BITS1, 2
SB1
SB2
SB3
PROTECTION DESCRIPTION
1
U
No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if
programmed.)
2
P
U
MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM
is disabled.
3
P
U
Same as 2, also verify is disabled.
4
P
Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES:
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
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