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參數(shù)資料
| 型號(hào)： | P56C3Q991-5J |
| 英文描述： | Eight Distributed-Output Clock Driver |
| 中文描述： | 八分布式輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 544K |
| 代理商： | P56C3Q991-5J |
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PI6C3Q991, PI6C3Q993
7
PS8449A 10/09/00
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Table 9. Switching Characteristics Over Operating Range
Notes:
1. All timing tolerances apply for F NOM
≥
25MHz. Guaranteed by design and characterization, not subject to 100%
production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t
U
delay
has been selected when all are loaded with the specified load.
3. t
SKEWPR
is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
U
.
4. t
SKEW0
is the skew between outputs when they are selected for 0t
U
.
5. There are 3 classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH),
and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
6. t DEV is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient
temperature, air flow, etc.)
7. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at REF or FB until t
PD
is within specified limits.
8. t
PD
is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
9. Measured at 2.0V.
10. Measured at 0.8V.
11. Refer to Table12 for more detail.
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