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參數(shù)資料
| 型號(hào)： | P4C422-35SMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | HIGH SPEED 256 x 4 STATIC CMOS RAM |
| 中文描述： | 256 X 4 STANDARD SRAM, 35 ns, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 219K |
| 代理商： | P4C422-35SMB |
1
Document #
SRAM101
REV. A
Revised October 2005
FEATURES
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
CMOS for Low Power
– 495 mW Max. – 10/12/15/20/25 (Commercial)
– 495 mW Max. – 15/20/25/35 (Military)
DESCRIPTION
The P4C422 is a 1,024-bit high-speed (10ns) Static
RAM with a 256 x 4 organization. The memory requires
no clocks or refreshing and has equal access and cycle
times. Inputs and outputs are fully TTL compatible.
Operation is from a single 5 Volt supply. Easy memory
expansion is provided by an active LOW chip select one
(
CS
) and active HIGH chip select two (CS
2
) as well as
3-state outputs.
P4C422
HIGH SPEED 256 x 4
STATIC CMOS RAM
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
In addition to high performance and high density, the
device features latch-up protection, single event and
upset protection. The P4C422 is offered in several
packages: 22-pin 400 mil DIP (plastic and ceramic), 24-
pin 300 mil SOIC, 24-pin square LCC and 24-pin
CERPACK. Devices are offered in both commercial and
military temperature ranges.
Single 5V±10% Power Supply
Separate I/O
Fully TTL Compatible Inputs and Outputs
Resistant to single event upset and latchup
resulting from advanced process and design
improvements
Standard 22-pin 400 mil DIP, 24-pin 300 mil
SOIC, 24-pin square LCC package and 24-pin
CERPACK package
SOIC (S4)
CERPACK (F3) SIMILAR
DIP (P3-1, C3-1, D3-1)
LCC (L4)
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