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參數(shù)資料
| 型號： | P4C198L-20PMB |
| 廠商： | Pyramid Semiconductor Corporation |
| 英文描述： | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| 中文描述： | 超高速16K的× 4靜態(tài)CMOS五羊 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 244K |
| 代理商： | P4C198L-20PMB |
P4C198/198L, P4C198A/198AL
Page 5 of 13
Document #
SRAM113
REV A
READ CYCLE NO. 2 (ADDRESS Controlled)
(5,6)
READ CYCLE NO. 3 (
CE
(12)
Controlled)
(5,7,8)
10. Read Cycle Time is measured from the last valid address
to the first transitioning address.
11. Transitions caused by a chip enable control have similar
delays irrespective of whether
CE
1
or
CE
2
causes them
(P4C198A/L).
12.
CE
1
,
CE
2
for P4C198A/L.
Notes:
6.
CE
(
CE
CE
for P4C198A/L) and
OE
are LOW READ cycle.
7.
OE
is LOW for the cycle.
8. ADDRESS must be valid prior to, or coincident with
CE
(
CE
1
and
CE
for P4C198A/L) transition LOW.
9. Transition is measured ± 200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
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