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參數(shù)資料
| 型號： | P4C198A-10CI |
| 廠商： | Pyramid Semiconductor Corporation |
| 英文描述： | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| 中文描述： | 超高速16K的× 4靜態(tài)CMOS五羊 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 244K |
| 代理商： | P4C198A-10CI |
P4C198/198L, P4C198A/198AL
Page 8 of 13
Document #
SRAM113
REV A
TRUTH TABLES
P4C198/L
P4C198A/L
CE
1
H
CE
2
X
WE
OE
Mode
Output
X
X
Standby
High Z
X
H
X
X
Standby
High Z
L
L
H
H
Output Inhibit
High Z
L
L
H
L
READ
D
OUT
D
IN
L
L
L
X
WRITE
CE
WE
OE
Mode
Output
H
X
X
Standby
High Z
L
H
H
Output Inhibit
High Z
L
H
L
READ
D
OUT
D
IN
L
L
X
WRITE
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C198/L and P4C198A/L, care
must be taken when testing this device; an inadequate setup can cause
a normal functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the V
and
ground planes directly up to the contactor fingers. A 0.01 μF high
Figure 1. Output Load
Figure 2. Thevenin Equivalent
frequency capacitor is also required between V
and ground. To avoid
signal reflections, proper termination must be used; for example, a 50
test environment should be terminated into a 50
load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116
resistor must
be used in series with D
OUT
to match 166
(Thevenin Resistance).
AC TEST CONDITIONS
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