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參數(shù)資料
| 型號(hào)： | P4C168L-35FSM |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 4K X 4 STANDARD SRAM, 35 ns, PDFP20 |
| 封裝： | DFP-20 |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大?。?/td> | 628K |
| 代理商： | P4C168L-35FSM |
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P4C168/P4C168L, P4C169, P4C170
Page 8 of 14
Document # SRAM107 REV E
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169 AND P4C170
care must be taken when testing these devices; an inadequate setup
can cause a normal functioning part to be rejected as faulty. Long
high-inductance leads that cause supply bounce must be avoided by
bringing the V
CC and ground planes directly up to the contactor fingers.
A high frequency capacitor of 0.01 F is also required between V
CC
Figure 1. Output Load
Figure 2. Thevenin Equivalent
AC TEST CONDITIONS
and ground. To avoid signal reflections, proper termination must be
used; for example, a 50 test environment should be terminated into
a 50 load with 1.73V (Thevenin Voltage) at the comparator input,
and a 116 resistor must be used in series with D
OUT to match 166
(Thevenin Resistance).
LCC PIN CONFIGURATION
LCC (L9)
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
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