參數(shù)資料
型號: P4C148-55CM
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS
中文描述: 1K X 4 STANDARD SRAM, 35 ns, CDIP18
封裝: 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-18
文件頁數(shù): 5/10頁
文件大?。?/td> 289K
代理商: P4C148-55CM
P4C148/P4C149
Page 5 of 10
Document #
SRAM104
REV B
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Mode
CE
WE
Output
Power
Standby
H
X
High Z
Standby
Read
L
H
D
OUT
High Z
Active
Write
L
L
Active
AC TEST CONDITIONS
TRUTH TABLE
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Due to the ultra-high speed of the P4C148/149, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the V
and ground
planes directly up to the contactor fingers. A 0.01 μF high frequency
capacitor is also required between V
and ground. To avoid signal
reflections, proper termination must be used; for example, a 50
test
environment should be terminated into a 50
load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116
resistor must be used in
series with D
OUT
to match 166
(Thevenin Resistance).
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