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參數(shù)資料
P4C148/P4C149
Page 4 of 10
Document #
SRAM104
REV B
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED)
(9)
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
high, the output remains in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first transition address.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
/
CS
CONTROLLED)
(9)
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
12
15
20
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Write Cycle Time
25
35
45
55
Chip Enable Time to End of Write
Address Valid to End of Write
8
8
10
10
12
12
16
16
20
20
25
25
30
30
35
35
Address Set-up Time
Write Pulse Width
0
8
0
10
0
12
0
16
0
20
0
25
0
30
0
35
Address Hold Time from End of Write
0
0
0
0
0
0
0
0
Data Valid to End of Write
Data Hold Time
5
0
6
0
7
0
9
0
12
0
16
0
20
0
25
0
Write Enable to Output in High Z
5
6
7
7
8
12
15
20
Output Active from End of Write
0
0
0
0
0
0
0
0
Sym
Parameter
-10
-12
-45
-55
-15
-20
-25
-35
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