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參數(shù)資料
| 型號(hào)： | P4C1281-20PM |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 4 STANDARD SRAM, 20 ns, PDIP28 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 862K |
| 代理商： | P4C1281-20PM |
Document # SRAM136 REV OR
Revised July 2009
P4C1281/P4C1282
ULTRA HIGH SPEED 64K X 4
cmoS STATIc RAmS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Industrial)
– 20/25/35/45 ns (Military)
Low Power Operation
5V ± 10% Power Supply
Separate Inputs and Outputs
– P4C1281 Input Data at Outputs during Write
– P4C1282 Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (P5, C5, D5-2), SOJ (J5)
DESCRIPTIOn
The P4C1281 and P4C1282 are 262,144-bit (64Kx4) ultra
high-speed static RAMs similar to the P4C1258, but with
separate data I/O pins. The P4C1281 features a transpar-
ent write operation; the outputs of the P4C1282 are in high
impedance during the write cycle. The RAMs operate from
a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
The P4C1281 and P4C1282 are available in 28-pin 300
mil DIP and SOJ, and a 28-pin 350x550 mil LCC providing
excellent board level densities.
LCC (L5)
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| P4C1281-25CI | 64K X 4 STANDARD SRAM, 25 ns, CDIP28 |
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| P4C1281-35PMB | 64K X 4 STANDARD SRAM, 35 ns, PDIP28 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| P4C1281-25CC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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| P4C1281-25CMB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| P4C1281-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| P4C1281-25LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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