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參數(shù)資料
| 型號： | P4C1258-35PI |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM |
| 中文描述： | 64K X 4 STANDARD SRAM, 35 ns, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 185K |
| 代理商： | P4C1258-35PI |
P4C1258
Page 6 of 9
Document #
SRAM123
REV OR
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Mode
CE
WE
Output
Power
Standby
H
X
High Z
Standby
Read
L
H
D
OUT
D
IN
Active
Write
L
L
Active
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1258, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the V
and
ground planes directly up to the contactor fingers. A 0.01 μF high
frequency capacitor is also required between V
and ground. To avoid
signal reflections, proper termination must be used; for example, a 50
test environment should be terminated into a 50
load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116
resistor must
be used in series with D
OUT
to match 166
(Thevenin Resistance).
Figure 1. Output Load
Figure 2. Thevenin Equivalent
AC TEST CONDITIONS
TRUTH TABLE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CONTROLLED)
(9)
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相關代理商/技術參數(shù) |
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| P4C1258-45CM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| P4C1258-45CMB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| P4C1258-45LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| P4C1258-45LMB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| P4C1258-55CM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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