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參數(shù)資料
| 型號： | P4C1049L-70L36MB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | HIGH SPEED 512K x 8 STATIC CMOS RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 70 ns, CDSO36 |
| 封裝： | 0.452 X 0.920 INCH, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 222K |
| 代理商： | P4C1049L-70L36MB |
P4C1049
Page 3 of 12
Document #
SRAM128
REV OR
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
I
CC
Symbol
Parameter
Temperature
Range
Commercial
Dynamic Operating Current*
Industrial
Military
–15
220
N/A
–20
185
–25
180
–35
N/A
–45
N/A
–55
N/A
–70
N/A
Unit
N/A
mA
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A
N/A
190
185
175
N/A
DATA RETENTION CHARACTERISTICS (P4C1049L Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Conditons
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V
or V
IN
≤
0.2V
Min
3.0
0
t
RC
§
Typ.*
V
CC
= 3.0V
Max
V
CC
= 3.0V
Unit
2
3
V
mA
ns
ns
*T
A
= +25°C
§t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
165
170
200
195
185
175
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