參數資料
型號: P4C1048L-55CWI
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: LOW POWER 512K x 8 CMOS STATIC RAM
中文描述: 512K X 8 STANDARD SRAM, 55 ns, CDIP32
封裝: 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
文件頁數: 5/12頁
文件大?。?/td> 168K
代理商: P4C1048L-55CWI
P4C1048L
Page 5 of 12
Document #
SRAM129
REV D
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
and
OE
are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
transition LOW.
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CE
CONTROLLED)
4. Transition is measured ± 200 mV from steady state voltage prior to change,
with loading as specified in Figure 1. This parameter is sampled and not
100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
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