參數(shù)資料
型號(hào): P4C1048L-45TMB
廠商: Pyramid Semiconductor Corporation
英文描述: LOW POWER 512K x 8 CMOS STATIC RAM
中文描述: 低功率為512k × 8的CMOS靜態(tài)RAM
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 168K
代理商: P4C1048L-45TMB
P4C1048L
Page 5 of 12
Document #
SRAM129
REV D
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
and
OE
are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
transition LOW.
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CE
CONTROLLED)
4. Transition is measured ± 200 mV from steady state voltage prior to change,
with loading as specified in Figure 1. This parameter is sampled and not
100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
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