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參數(shù)資料
| 型號(hào)： | P4C1041-20TI |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 20 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 453K |
| 代理商： | P4C1041-20TI |
P4C1041
Page 7 of 10
Document #
SRAM133
REV OR
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST CONDITIONS
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1041, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the V
and
ground planes directly up to the contactor fingers. A 0.01 μF high
frequency capacitor is also required between V
CC
and ground. To avoid
signal reflections, proper termination must be used; for example, a 50
test environment should be terminated into a 50
load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116
resistor must
be used in series with D
OUT
to match 166
(Thevenin Resistance).
Active
TRUTH TABLE
Standby
Active
Power
I/O
0
- I/O
7
High Z
WE
OE
CE
D
OUT
D
OUT
High Z
D
IN
D
IN
X
H
H
H
L
X
L
L
L
X
H
L
L
L
L
Active
Active
BHE
BLE
X
L
H
L
L
X
L
L
H
L
I/O
8
- I/O
15
High Z
D
OUT
High Z
D
OUT
D
IN
High Z
Read Upper Bits Only
Power-down
Read All Bits
Mode
Read Lower Bits Only
Write All Bits
L
X
L
Active
H
L
Write Lower Bits Only
High Z
High Z
L
H
X
H
L
L
Active
Active
L
X
H
X
D
IN
Write Upper Bits Only
Selected, Outputs Disabled
High Z
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