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參數(shù)資料
| 型號： | P32P4911A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
| 中文描述： | 1 CHANNEL READ CHANNEL, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 4/63頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P32P4911A |
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1996 Jul 25
4
Philips Semiconductors
Product specification
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
P32P4911A
Automatic Gain Control:
Dual mode AGC, analog during acquisition, sampled during data reads
Separate AGC level storage pins for data and servo
Dual rate attack and decay charge pump for rapid AGC recovery (analog)
Programmable, symmetric, charge pump currents for data reads (sampled)
Charge pump currents track programmable data rate during data reads (sampled)
Low drift AGC hold circuitry
Low-Z circuitry at AGC input provides for rapid external coupling capacitor recovery
AGC Amplifier squelch during Low-Z
Wide bandwidth, precision full-wave rectifier
Programmable AGC controls
– Separate external input pins for AGC hold, fast recovery, and Low-Z control
or
– Internal Low-Z and fast decay timing for rapid transient recovery and AGC acquisition. Timing set with external
resistors (2). Ultra fast decay current set with external resistor. AGC input impedance vs LOWZ = 5:1.
2-bit DAC to control AGC voltage in servo mode between 1.1 and 1.4 V
Filter/Equalizer:
Programmable, 7-pole, continuous time filter provides:
– Channel filter and pulse slimming equalization for equalization to PR4
– Programmable cutoff frequency from 4 to 34 MHz
– Programmable boost /equalization of 0 to 13 dB
– Programmable "zeros" equalization provides time asymmetry compensation
–
±
0.5 ns group delay variation from 0.3c to c, with c = 34 MHz
– Minimizes size and power
– Low-Z switch at filter output for fast offset recovery
– No external coupling capacitors required
– DC offset compensation provided at filter output
– Five tap transversal filter for fine equalization to PR4
– Self adapting inner taps (symmetric)
– Programmable outer taps (symmetric, 4-bits)
– Equalization hold input
– "Zeros" channel quality output
– Amplitude asymmetry factor output
Pulse Qualification:
Sampled Viterbi qualification of signal equalized to PR4
Register programmable window or hysteresis pulse qualifier for servo reads
Selectable RDS pulse width and polarity for servo gray code reads
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