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| 型號(hào)： | P312XDP512J1VAA |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Covers, S12XD, S12XB & S12XA Families |
| 中文描述： | 封面，S12XD，S12XB |
| 文件頁(yè)數(shù)： | 887/1350頁(yè) |
| 文件大?。?/td> | 3951K |
| 代理商： | P312XDP512J1VAA |
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
887
22.4.3
Pin Interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (
Figure 22-78
) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (
Figure 22-77
and
Table 22-69
).
Figure 22-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
Figure 22-78. Pulse Illustration
Table 22-69. Pulse Detection Criteria
Pulse
Mode
STOP
Unit
STOP
1
1
These values include the spread of the oscillator frequency over temperature,
voltage and process.
Ignored
Uncertain
Valid
t
pulse
≤
3
3 < t
pulse
< 4
t
pulse
≥
4
Bus clocks
Bus clocks
Bus clocks
t
pulse
≤
t
pign
t
pign
< t
pulse
< t
pval
t
pulse
≥
t
pval
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
t
pign
t
pval
uncertain
t
pulse
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| P312XDP512J1VAAR | Covers, S12XD, S12XB & S12XA Families |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P312XDP512J1VAAR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
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