
Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
MC9S12XDP512 Data Sheet, Rev. 2.17
550
Freescale Semiconductor
13.3.0.9
PIT Count Register 0 to 3 (PITCNT0–3)
Read: Anytime
Write: Has no meaning or effect
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R PCNT
W
Reset
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCNT
9
PCNT
8
PCNT
7
PCNT
6
PCNT
5
PCNT
4
PCNT
3
PCNT
2
PCNT
1
PCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-15. PIT Count Register 0 (PITCNT0)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R PCNT
W
Reset
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCNT
9
PCNT
8
PCNT
7
PCNT
6
PCNT
5
PCNT
4
PCNT
3
PCNT
2
PCNT
1
PCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-16. PIT Count Register 1 (PITCNT1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R PCNT
W
Reset
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCNT
9
PCNT
8
PCNT
7
PCNT
6
PCNT
5
PCNT
4
PCNT
3
PCNT
2
PCNT
1
PCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-17. PIT Count Register 2 (PITCNT2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R PCNT
W
Reset
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCNT
9
PCNT
8
PCNT
7
PCNT
6
PCNT
5
PCNT
4
PCNT
3
PCNT
2
PCNT
1
PCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-18. PIT Count Register 3 (PITCNT3)
Table 13-9. PITCNT0–3 Field Descriptions
Field
Description
15:0
PCNT[15:0]
PIT Count Bits 15-0
— These bits represent the current 16-bit modulus down-counter value. The read access
for the count register must take place in one clock cycle as a 16-bit access.