NOTE
PS[7:4] are not available in 80-pin packages.
23.0.7.8
Port M
This port is associated with the CAN40 and SPI0. Port M pins PM[7:0] can be used for either
general purpose I/O, or with the CAN, SCI and SPI subsystems.
The CAN0, CAN4 and SPI0 pins can be re-routed.
Refer to
Section 23.0.5.37, “Module Routing
Register (MODRR)”
.
NOTE
PM[7:6] are not available in 80-pin packages.
23.0.7.9
Port P
This port is associated with the PWM, SPI1 and SPI2. Port P pins PP[7:0] can be used for either
general purpose I/O, or with the PWM and SPI subsystems.
The pins are shared between the PWM channels and the SPI1 and SPI2. If the PWM is enabled the
pinsbecomePWMoutputchannelswiththeexceptionofpin7whichcanbePWMinputoroutput.
If SPI1 or SPI2 are enabled and PWM is disabled, the respective pin configuration is determined
by status bits in the SPI.
The SPI1 and SPI2 pins can be re-routed.
Refer to
Section 23.0.5.37, “Module Routing Register
(MODRR)”
.
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion
(
Section 23.0.8, “Pin Interrupts
”
).
NOTE
PP[6] is not available in 80-pin packages.
23.0.7.10 Port H
This port is associated with the SPI1, SPI2, SCI4. Port H pins PH[7:0] can be used for either
general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed
SPI1 and SPI2.
Refer to
Section 23.0.5.37, “Module Routing Register (MODRR)”
.
Port H offers 8 I/O pins with edge triggered interrupt capability (
Section 23.0.8, “Pin Interrupts
”
).
NOTE
Port H is not available in 80-pin packages.
23.0.7.11 Port J
ThisportisassociatedwiththechipselectsCS0,CS1,CS2andCS3aswellaswithCAN4,CAN0,
IIC1, IIC0, and SCI2. Port J pins PJ[7:4] and PJ[2:0] can be used for either general purpose I/O, or
with the CAN, IIC, or SCI subsystems. If IIC takes precedence the associated pins become IIC