Chapter 1 Device Overview MC9S12XD-Family
MC9S12XDP512 Data Sheet, Rev. 2.17
52
Freescale Semiconductor
1.2.2
Signal Properties Summary
Table 1-7
summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts
of the S12XD, S12XB and S12XA family please refer to
Appendix E Derivative Differences
.
Table 1-7. Signal Properties Summary (Sheet 1 of 4)
Pin
Name
Function 1
Pin
Name
Function 2
Pin
Name
Function 3
Pin
Name
Function 4
Pin
Name
Function 5
Power
Supply
Internal Pull
Resistor
Description
CTRL
Reset
State
EXTAL
XTAL
RESET
TEST
VREGEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
DDPLL
V
DDPLL
V
DDR
N.A.
V
DDX
NA
NA
NA
NA
Oscillator pins
PULLUP
External reset
RESET pin
PUCR
DOWN Test input
Up
Voltage regulator enable
Input
NA
PLL loop filter
Up
Background debug
Disabled Port AD I/O, Port AD inputs
of ATD1 and
analog inputs of ATD1
Disabled Port AD I/O, Port AD inputs
of ATD0 and
analog inputs of ATD0
Disabled Port A I/O
Disabled Port BI/O
Disabled Port A I/O, address bus,
internal visibility data
Disabled Port B I/O, address bus,
internal visibility data
Disabled Port B I/O, address bus,
upper data strobe
Disabled Port C I/O, data bus
Disabled Port D I/O, data bus
Up
Port E I/O, system clock
output, clock select
While RESET
pin is low: down
input
While RESET
pin is low: down
mode input, tag low input
PUCR
Up
Port E I/O, bus clock output
PUCR
Up
Port E I/O, low byte data
strobe, EROMON control
PUCR
Up
Port E I/O, read/write
PUCR
Up
Port E Input, maskable
interrupt
XFC
BKGD
PAD[23:08]
—
—
—
—
—
—
—
—
—
—
V
DDPLL
V
DDX
V
DDA
NA
MODC
AN[23:8]
Always on
PER0/
PER1
PAD[07:00]
AN[7:0]
—
—
—
V
DDA
PER1
PA[7:0]
PB[7:0]
PA[7:0]
—
—
—
—
—
—
—
—
—
—
V
DDR
V
DDR
V
DDR
PUCR
PUCR
PUCR
ADDR[15:8]
IVD[15:8]
PB[7:1]
ADDR[7:1]
IVD[7:0]
—
—
V
DDR
PUCR
PB0
ADDR0
UDS
V
DDR
PUCR
PC[7:0]
PD[7:0]
PE7
DATA[15:8]
DATA[7:0]
ECLKX2
—
—
—
—
—
—
—
—
V
DDR
V
DDR
V
DDR
PUCR
PUCR
PUCR
XCLKS
PE6
TAGHI
MODB
—
—
V
DDR
Port E I/O, tag high, mode
PE5
RE
MODA
TAGLO
—
V
DDR
Port E I/O, read enable,
PE4
PE3
ECLK
LSTRB
—
LDS
—
—
—
V
DDR
V
DDR
EROMCTL
PE2
PE1
R/W
IRQ
WE
—
—
—
—
—
V
DDR
V
DDR