- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383732 > P312XDP512F0MFU (飛思卡爾半導(dǎo)體(中國)有限公司) Covers, S12XD, S12XB & S12XA Families PDF資料下載
參數(shù)資料
| 型號(hào)： | P312XDP512F0MFU |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Covers, S12XD, S12XB & S12XA Families |
| 中文描述： | 封面，S12XD，S12XB |
| 文件頁數(shù)： | 798/1350頁 |
| 文件大?。?/td> | 3951K |
| 代理商： | P312XDP512F0MFU |
Chapter 21 External Bus Interface (S12XEBIV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
798
Freescale Semiconductor
21.4.2.2.3
Read-Write-Read Access Timing
21.4.2.3
Internal Visibility Data
Dependingontheaccesssizeandalignment,eitherawordofreaddataismadevisibleontheaddresslines
or only the related data byte will be presented in the ECLK low phase. For details refer to
Table 21-16
.
21.4.3
Accesses to Port Replacement Registers
AllreadandwriteaccessestoPRRaddressestaketwobusclockcyclesindependentoftheoperatingmode.
If writing to these addresses in emulation modes, the access is directed to both, the internal register and
the external resource while reads will be treated external.
The XEBI control registers also belong to this category.
21.4.4
Stretched External Bus Accesses
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI
supports stretched external bus accesses (wait states).
This feature is available in normal expanded mode and emulation expanded mode for accesses to all
external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2
cycles, respectively.
Table 21-15. Interleaved Read-Write-Read Accesses (1 Cycle)
Access #0
1
high
Access #1
2
high
Access #2
3
high
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
R/W
...
...
...
...
low
acc 0
iqstat -1
z
z
1
low
acc 1
iqstat 0
ivd 0
(write) data 1
(write) data 1
0
low
acc 2
iqstat 1
x
z
z
1
...
...
...
...
...
...
...
addr 0
addr 1
addr 2
...
...
...
...
1
z
data 0
0
1
Table 21-16. IVD Read Data Output
Access
IVD[15:8]
IVD[7:0]
Word read of data at an even and even+1 address
Word read of data at an odd and odd+1 internal RAM address (misaligned)
Byte read of data at an even address
Byte read of data at an odd address
ivd(even)
ivd(odd+1)
ivd(even)
addr[15:8] (rep.)
ivd(even+1)
ivd(odd)
addr[7:0] (rep.)
ivd(odd)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P312XDP512F0MFUR | Covers, S12XD, S12XB & S12XA Families |
| P312XDP512F0MFV | Covers, S12XD, S12XB & S12XA Families |
| P312XDP512F0MFVR | Covers, S12XD, S12XB & S12XA Families |
| P312XDP512F0MPV | Covers, S12XD, S12XB & S12XA Families |
| P312XDP512F0MPVR | Covers, S12XD, S12XB & S12XA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P312XDP512J1VAAR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| P3-13 | 制造商:ITT Interconnect Solutions 功能描述:P3-13 - Bulk |
| P3130 | 制造商:Switchcraft 功能描述: |
| P31-300 | 制造商:SEMIKRON 制造商全稱:Semikron International 功能描述:For stud devices |
| P313-001 | 制造商:Tripp Lite 功能描述:MINI STEREO DUBBING CORD Y ADAPTER 3.5MM M TO (2) 3.5MM F - - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。