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型號(hào)：	P312XDP512F0MAG
廠商：	飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述：	Covers, S12XD, S12XB & S12XA Families
中文描述：	封面，S12XD，S12XB
文件頁(yè)數(shù)：	590/1350頁(yè)
文件大?。?/td>	3951K
代理商：	P312XDP512F0MAG

Chapter 15 Background Debug Module (S12XBDMV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

Figure 15-14

shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could

occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.

ConsiderthatthetargetCPUisexecutingapendingBDMcommandattheexactmomentthePODisbeing

connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this

case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not

a probable situation, the protocol does not prevent this conflict from happening.

Figure 15-14. ACK Pulse and SYNC Request Conflict

ThisinformationisbeingprovidedsothattheMCUintegratorwillbeaware

that such a conflict could eventually occur.

The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE

BDM commands. This provides backwards compatibility with the existing POD devices which are not

able to execute the hardware handshake protocol. It also allows for new POD devices, that support the

hardware handshake protocol, to freely communicate with the target device. If desired, without the need

for waiting for the ACK pulse.

The commands are described as follows:

ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse

when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the

ACK pulse as a response.

ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst

case delay time at the appropriate places in the protocol.

The default state of the BDM after reset is hardware handshake protocol disabled.

All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then

readyforreadingoutbytheBKGDserialpin.AllthewritecommandswillACK(ifenabled)afterthedata

has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See

Section 15.4.3,“BDMHardwareCommands”

Section 15.4.4,“StandardBDMFirmwareCommands”

for more information on the BDM commands.

(Target MCU)

Speedup Pulse

High-Impedance

Host SYNC Request Pulse

At Least 128 Cycles

Electrical Conflict

Target Drive

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