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參數(shù)資料
| 型號： | P3057LD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| 中文描述： | N溝道增強模式的邏輯電平場效應(yīng)晶體管 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 216K |
| 代理商： | P3057LD |
2
APR-14-2003
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3057LD
TO-252 (DPAK)
NIKO-SEM
V
GS
= 5V, I
D
= 12A
70
115
Drain-Source On-State
Resistance
1
R
DS(ON)
V
GS
= 10V, I
D
= 12A
48
85
m
Ω
Forward Transconductance
1
g
fs
V
DS
= 15V, I
D
= 12A
16
S
DYNAMIC
Input Capacitance
C
iss
450
Output Capacitance
C
oss
200
Reverse Transfer Capacitance
C
rss
V
GS
= 0V, V
DS
= 15V, f = 1MHz
60
pF
Total Gate Charge
2
Q
g
15
Gate-Source Charge
2
Q
gs
2.0
Gate-Drain Charge
2
Q
gd
V
DS
= 0.5V
(BR)DSS
, V
GS
= 10V,
I
D
= 6A
7.0
nC
Turn-On Delay Time
2
t
d(on)
6.0
Rise Time
2
t
r
V
DS
= 15V, R
L
= 1
Ω
6.0
Turn-Off Delay Time
2
t
d(off)
I
D
12A, V
GS
= 10V, R
GS
= 2.5
Ω
20
Fall Time
2
t
f
5.0
nS
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T
C
= 25
°
C)
Continuous Current
I
S
12
Pulsed Current
3
I
SM
20
A
Forward Voltage
1
V
SD
I
F
= I
S
, V
GS
= 0V
1.5
V
Reverse Recovery Time
t
rr
30
nS
Peak Reverse Recovery Current
I
RM(REC)
I
F
= I
S
, dl
F
/dt = 100A /
μ
S
15
A
Reverse Recovery Charge
Q
rr
0.043
μ
C
1
Pulse test : Pulse Width
≤
300
μ
sec, Duty Cycle
≤
2%.
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P3057LD”, DATE CODE or LOT #
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