參數(shù)資料
型號: P3000AA61RP
英文描述: MCU CMOS 44LD LOW PWR, -40C to +85C, 44-QFN, T/R
中文描述: SIDAC的| 330V五(公報)最大| 800mA的我(縣)|對220VAR
文件頁數(shù): 86/161頁
文件大?。?/td> 986K
代理商: P3000AA61RP
ITU-T K.20 and K.21
SIDACtor
Data Book
4 - 12
Teccor Electronics
(972) 580-7777
External Protectors
For equipment being tested to the exposed level, it is standard practice for external
line protectors (typically gas tubes) to be used in order to handle the large surge
currents generated during K.20 and K.21 qualification. Realizing that these protectors
can affect the characteristics of the EUT, it is important that the protectors used be
agreed upon by the principal parties involved (the equipment supplier and testing
administrator). Once agreed upon, the protectors should be used when primary
protection is specified, and allowance should be given for a new set of protectors after
the completion of each test sequence.
Note:
An alternative to using external protectors is for the test administrator to simulate the
conditions expected (as if the external protectors were used) by modifying the surges
found in K.20 and K.21.
Equipment Boundaries
Because of the numerous types of equipment, during K.20 and K.21 testing ITU-T
looks at each EUT as a
black box
with three terminals (A, B, and E). The applicant is
expected to define the boundaries of this
black box
, and in doing so, should be aware
that any protective device within these boundaries is considered an unchangeable part
of that piece of equipment.
Permitted Malfunction or Damage
During K.20 and K.21 qualification, ITU-T recognizes two levels of malfunction or
damage to the EUT:
Level A states that equipment withstands the test without damage or disturbance
and operates properly after the test. If specifically permitted, the administration
may accept the opening of the fuse.
Level B states that a fire hazard does not occur in the equipment as a result of the
test, and that any permanent damage or malfunction is confined to a small number
of external line interface circuits (as defined by the test administrator).
The acceptable level of malfunction for each test is specified under Acceptance
Criteria.
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