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參數(shù)資料
| 型號： | P2V28S30ATP-8 |
| 廠商： | Vanguard International Semiconductor Corporation |
| 英文描述： | 128Mb SDRAM Specification |
| 中文描述： | 128Mb的SDRAM內存規(guī)格 |
| 文件頁數(shù)： | 5/51頁 |
| 文件大?。?/td> | 652K |
| 代理商： | P2V28S30ATP-8 |
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128Mb Synchronous DRAM
JULY.2000
Rev.2.2
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-4
PIN FUNCTION
CLK
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
CKE
Input
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
/CS
Input
Chip Select:
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
Input / Output
Input
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
Data In and Data out are referenced to the rising edge of CLK.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
DQM(x4,x8),
DQMU/L(x16)
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