參數(shù)資料
型號(hào)： P2V28S20ATP-75
廠商： Vanguard International Semiconductor Corporation
英文描述： 128Mb SDRAM Specification
中文描述： 128Mb的SDRAM內(nèi)存規(guī)格
文件頁(yè)數(shù)： 2/51頁(yè)
文件大?。?/td> 652K
代理商： P2V28S20ATP-75
JULY.2000
Rev.2.2
128Mb Synchronous DRAM
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
DESCRIPTION
P2V28S20ATP is organized as 4-bank x 8,388,608-word x
4-bit Synchronous DRAM with LVTTL interface and
P2V28S30ATP is organized as 4-bank x 4,194,304-word x
8-bit and P2V28S40ATP is organized as 4-bank x 2,097,
152-word x 16-bit. All inputs and outputs are referenced to
the rising edge of CLK.
P2V28S20ATP-7,-75,-8
(4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8
(4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8
(4-BANK x 2,097,152-WORD x 16-BIT)
Page-1
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (P2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
P2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
PRELIMINARY
Some of contents are described for general products and
are subject to change without notice.
P2V28S20ATP,P2V28S30ATP and P2V28S40ATP
achieve very high speed data rates up to 166MHz, and are
suitable for main memories or graphic memories in com-
puter systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle Time
Active to Precharge Command Period (Min.)
Row to Column Delay
Access Time from CLK
Ref /Active Command Period
Operation Current (Single Bank)
Self Refresh Current
V28S20D
V28S30D
V28S40D
CL=2
CL=3
CL=2
CL=3
(Min.)
(Min.)
(Max.)
(Max.)
(Min.)
(Max.)
-7
85mA
85mA
85mA
63ns
20ns
-
5.4ns
45ns
7ns
-
1mA
-75
10ns
7.5ns
85mA
85mA
85mA
1mA
67.5ns
45ns
20ns
6ns
5.4ns
-8
10ns
8ns
70ns
48ns
20ns
6ns
6ns
85mA
85mA
85mA
1mA
-7,-75,-8
P2V28S20/30/40ATP
相關(guān)PDF資料
PDF描述
P2V28S20ATP-8 128Mb SDRAM Specification
P2V28S20DTP-7 128Mb SDRAM Specification
P2V28S30ATP-7 128Mb SDRAM Specification
P2V28S30ATP-75 128Mb SDRAM Specification
P2V28S30ATP-8 128Mb SDRAM Specification
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P2V28S20ATP-8 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S20DTP-7 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S30ATP-7 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S30ATP-75 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
P2V28S30ATP-8 制造商:VML 制造商全稱:VML 功能描述:128Mb SDRAM Specification
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