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參數(shù)資料
| 型號(hào)： | P1P3800AG12CRTWG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR 12-WQFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | * |
| PLL： | 無 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 120Hz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 12-WQFN（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | P1P3800AG12CRTWGOSDKR |
Semiconductor Components Industries, LLC, 2012
January, 2012 Rev. 1
1
Publication Order Number:
P1P3800A/D
P1P3800A
Phase Synchronizing Clock
Generator
Product Description
P1P3800A is a Phase Synchronizing clock generator that generates
four outputs from an input clock. Output frequency will be a divide by
two of the input clock. The phase of the output clocks is selectable
through four select signals S1, S2, S3 and S4. Refer to Output Clock
Selection Table. The outputs will go ‘low’ when all the select signals
are ‘low’. The transition to a new state of the output will be ‘glitch
free’ when the select inputs change state. A Power Down signal
enables the device to be driven to a power save mode, when active.
The device works over a supply voltage range of 3.8 V 5.5 V. The
device is available in a 12Lead 3mmx3mm WQFN package and
operates over -40
°C to +85°C.
Features
Input Clock Frequency:
120 Hz 240 Hz (External Reference Clock)
Output Clock Frequency:
60 Hz 120 Hz
4 Clock Outputs
4 Two Level Controls to Select Sets of Clock Outputs
Output Buffer Drive Strength: 8 mA
Supply Voltage: 3.8 V 5.5 V
Power Down for Power Save
12Lead 3mmx3mm WQFN Package
Operating Temperature Range: -40°C to +85°C
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Application
P1P3800A can be used in applications where Phase Synchronization
is needed.
VDD
GND
CLKIN
Digital Logic
& Divider
S [1:4]
PD#
CLKOUT [1:4]
Figure 1. Block Diagram
WQFN12
CASE 510AH
MARKING
DIAGRAM
http://onsemi.com
PD#
CLKOUT4
CLKOUT3
S1
CLKIN
S2
PIN CONFIGURATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
P1P
3800A
ALYWG
G
12
11
10
9
56
7
4
8
3
CLKOUT2
1
2
1
S4
GND
S3
V
CLKOUT1
(Note: Microdot may be in either location)
P1P3800A
(TopView)
DD
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