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參數(shù)資料
| 型號(hào)： | P10C68-IGDCBS |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| 中文描述： | 的CMOS / SNOS非易失性SRAM的高性能8畝× 8非易失性靜態(tài)RAM的 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | P10C68-IGDCBS |
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P10C68/P11C68
12
Notes
22
21, 22
21, 22
21, 22
21, 22
21, 22
20
21, 22
21, 22
21, 22
21, 22
21, 22
21
Power
Standby
Active
Active
Active
I
CC2
Active
I/O
Output High Z
Output data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Mode
Not selected
Read RAM
Write RAM
Read RAM
Read RAM
Read RAM
Read RAM
Read RAM
Non-volatile STORE
Read RAM
Read RAM
Read RAM
Read RAM
Read RAM
Non-volatile RECALL
A
12
-A
0
(hex)
X
X
X
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
E
H
L
L
L
L
W
X
H
L
H
H
Standard
t
AVAV
t
AXAV
t
AVQZ
t
AVEL
t
ELEH
t
EHAX
Alternative
t
ACS
t
SKEW
t
ELQZ
t
STORE
t
RECALL
t
AE
t
EP
t
EA
Parameter
Read cycle time
Skew between sequentially
adjacent addresses
Address valid to output inactive
Store cycle time
Recall cycle time
Address set-up to chip enable
Chip enable pulse width
Chip disable to address change
Units
ns
ns
ns
ms
μ
s
ns
ns
ns
Notes
23
25
26
26, 30
27
27
27
Symbol
Min.
45
0
45
0
Max.
5
75
10
20
Min.
35
0
35
0
Max.
5
75
10
20
P11C68-45
P11C68-35
NOTES
23.
24.
Skew spec may be avoided by using E (bar) (STORE/RECALL CYCLE 2).
W (bar)
≥
V
IH
during entire address sequence to initiate a non-volatile cycle.
Required address sequences are shown in the Mode Selection table.
Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Measured with W (bar) high, G (bar) low and E (bar) low. Note that STORE cycles (but not RECALLS) are aborted by Vcc
< 3.3V (STORE Inhibit).
E (bar) must make the transition between V
IH
(max) to V
IL
(max), or V
IL
(max) to V
IH
(min) in a monotonic fashion.
Chip is continuously selected with E (bar) low.
Addresses 1 through 6 are found in the Mode Selection table. Address 6 determines whether the P11C68 performs a
STORE or RECALL. A RECALL cycle is performed automatically at power up when V
CC
exceeds 3.3V. V
CC
must not drop
below 3.3V once it has exceeded it for the RECALL to function properly, t
RECALL
is measured from the point at which V
CC
exceeds 3.3V.
Address transitions may not occur on any address pin during this time.
25.
26.
27.
28.
29.
30.
NOTES
21.
The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or
(0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W (bar) must be high during all six consecutive cycles. See
STORE CYCLE and RECALL CYCLE tables and diagrams for further details.
I/O state assumes that G (bar)
≥
V
IL
. Activation of non-volatile cycles does not depend on the state of G (bar).
22.
STORE / RECALL CYCLES 1 AND 2
(See notes 24 and 29)
NON-VOLATILE MEMORY OPERATION OF P11C68
MODE SELECTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P10C68-IGDPBS | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P11C68 | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P11C68- | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P11C68-35 | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P10C68-IGDPBS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
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| P10CU-0505Z | 制造商:PEAK 制造商全稱:PEAK electronics GmbH 功能描述:1KV ISOLATED 2W UNREGULATED DUAL OUTPUT SIP7 |
| P10CU-0512E | 制造商:PEAK 制造商全稱:PEAK electronics GmbH 功能描述:1KV ISOLATED 2W UNREGULATED SINGLE OUTPUT SIP7 |
| P10CU-0512Z | 制造商:PEAK 制造商全稱:PEAK electronics GmbH 功能描述:1KV ISOLATED 2W UNREGULATED DUAL OUTPUT SIP7 |
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