參數(shù)資料
型號(hào): P048F048M24AL
廠商: Vicor Corporation
元件分類: DC/DC變換器
英文描述: VI Chip - PRM-AL Pre-regulator Module
中文描述: 六芯片-大羅馬尼亞黨鋁預(yù)穩(wěn)壓模塊
文件頁數(shù): 8/15頁
文件大?。?/td> 544K
代理商: P048F048M24AL
vicorpower.com
800-735-6200
VI Chip Pre-Regulator Module
P048K048T24AL
Rev. 1.4
Page 8 of 15
PRELIMINARY
Pin / Control Functions
VI Chip Pre-Regulator Module
+IN / -IN DC Voltage Ports
The VI Chip maximum input voltage should not be exceeded. PRMs
have internal over / undervoltage lockout functions that prevent
operation outside of the specified input range. PRMs will turn on
when the input voltage rises above its undervoltage lockout. If the
input voltage exceeds the overvoltage lockout, PRMs will shut down
until the overvoltage fault clears.
+OUT / -OUT Factorized Voltage Output Ports
These ports provide the Factorized Bus voltage output. The –OUT port
is connected internally to the –IN port through a current sense resistor.
The PRM has a maximum power and a maximum current rating and is
protected if either rating is exceeded. Do not short –OUT to –IN.
VC – VTM Control
The VTM Control (VC) port supplies an initial V
CC
voltage to
downstream VTMs, — enabling the VTMs and synchronizing the rise of
the VTM output voltage to that of the PRM. The VC port also provides
feedback to the PRM to compensate for voltage drop due to the VTM
output resistance. The PRM’s VC port should be connected to the VTM
VC port. A PRM VC port can drive a maximum of two (2) VTM VC ports.
PC – Primary Control
The PRM voltage output is enabled when the PC pin is open circuit
(floating). To disable the PRM output voltage, the PC pin is pulled low.
Open collector optocouplers, transistors, or relays can be used to
control the PC pin. When using multiple PRMs in a high power array,
the PC ports should be tied together to synchronize their turn on.
TM – Factory Use Only
IL – Current Limit Adjust
The PRM has a preset, maximum, current limit set point. The IL port
may be used to reduce the current limit set point to a lower value.
PR – Parallel Port
The PR port signal, which is proportional to the PRM output power,
supports current sharing among PRMs. To enable current sharing, PR
ports should be interconnected. Bypass capacitance should be used
when interconnecting PR ports and steps should be taken to minimize
coupling noise into the interconnecting bus. Please consult Vicor
Applications Engineering regarding additional considerations.
VH – Auxiliary Voltage
VH is a gated, non-isolated, nominally 9 Volt, regulated DC voltage
(see “Auxiliary Pins” specifications, on Page 6) that is referenced to
SG. VH may be used to power external circuitry having a total current
consumption of no more than 5 mA.
SC – Secondary Control
The load voltage may be controlled by connecting a resistor or voltage
source to the SC port. The slew rate of the output voltage may be
controlled by controlling the rate-of-rise of the voltage at the SC port
(e.g., to limit inrush current into a capacitive load).
SG – Signal Ground
This port provides a low inductance Kelvin connection to –IN and
should be used as reference for the OS, CD, SC, and IL ports.
OS – Output Set
The application-specific value of the Factorized Bus voltage (Vf) is set
by connecting a resistor between OS and SG. Resistor value selection is
shown in Table 1 on Page 2, and described on Page 9. If no resistor is
connected, the PRM output will be approximately one volt.
CD – Compensation Device
Adaptive Loop control is configured by connecting an external resistor
between the CD port and SG. Selection of an appropriate resistor
value (see Equation 2 on Page 9 and Table 1 on Page 2) configures the
PRM to compensate for voltage drops in the equivalent output
resistance of the VTM and the PRM-VTM distribution bus. If no resistor
is connected to CD, the PRM will be in Local Loop mode and will
regulate the +OUT / –OUT voltage to a fixed value.
Signal Name
+In
–In
VC
PC
TM
IL
PR
VH
SC
SG
OS
CD
+Out
–Out
BGA Designation
P1-AA1,P2-AA2
AD1-AL1, AD2-AL2
A1,A2
C1, C2
E1, E2
G1, G2
L1, L2
A3, A4
C3, C4
E3, E4
G3, G4
L3, L4
P3-AA3, P4-AA4
AD3-AL3, AD4-AL4
Figure 13
— BGA configuration
Bottom View
4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
+Out
–Out
+In
–In
VC
PC
TM
IL
VH
SC
PR
NC
SG
OS
NC
CD
VS
FB
FG
NC
NC
NC
IF Version
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AL Version
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