
OZ992
OZ992-SF-1.7
Page 2
PIN DIAGRAM
PIN DESCRIPTION
Name
SMBCLK
SMBDATA
PWRGD
Pin No.
1
SMBus Clock Input for SMBus protocol communication.
2
I/O
SMBus Data Input/Output for SMBus protocol communication.
3
I
TTL
This pin indicates that the host system
’
s power, including the Core Logic chipsets, is stable. Before the host
system
’
s power is stable, this input pin will tri-state all the output pins from OZ992.
4
I
TTL
-
The embedded controller will signify the OZ992 when the activated SCI has been serviced. This pin is to be
used with EC master mode only.
[6:5]
I/O
TTL
4mA
Fully programmable GPIOs that can be used for a variety of dedicated or specific functions. Pins GPIO[17:16]
default as inputs. They are programmable to function as either GPI[17:16] inputs or GPO[17:16] outputs. Refer
to GPIO[19:16] Config.1&2 Registers for more details and GPIO Config. Tables (section 5.0) for input/output
selections.
[8:7]
I/O
TTL
4mA
Type
I
Input
TTL
Drive
-
Definition
SMBus Clock Input
TTL
12mA
SMBus Data Input/Output
-
Host System Power Good
EOI#
End of Interrupt
GPIO[17:16]
General Purpose I/Os
GPIO[19:18] /
TEST[1:0]
General Purpose I/Os
Fully programmable GPIOs that can be used for a variety of dedicated or specific functions. Pins
GPIO[19:18]/TEST[1:0] default as inputs. They are programmable to function as either GPI[19:18] inputs or
GPO[19:18] outputs. Refer to GPIO[19:16] Config.1&2 Registers for more details and GPIO Config. Tables
(section 5.0) for input/output selections.
During regular usage, pull-ups of
47K
should be connected to GPIO[19:18]/TEST[1:0] to ensure the regular
OZ992 operation. Alternative uses for GPIO[19:18] are as TEST[1:0], which provide 2 proprietary OZ992 test
modes.
SMBCLK
SMBDATA
PWRGD
EOI#
GPIO[16]
GPIO[17]
GPIO[18]/TEST[0]
GPIO[19]/TEST[1]
GPIO[0]/SMIEVENT
GPIO[1]
GPIO[2]/SMBALERT#
GPIO[3]
GPIO[4]
GND
VCC
32KHZ
RESETN
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
GPIO[9]
GPIO[8]
GPIO[7]
GPIO[6]
GPIO[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15