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參數(shù)資料
| 型號(hào)： | OZ6812 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ACPI CardBus Controller |
| 中文描述： | ACPI的CardBus控制器 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 105K |
| 代理商： | OZ6812 |
OZ6812
OZ6812-SF-1.5
Page 5
Pin Number
LQFP
36
Pin Name
Description
BGA
L3
Input
Type
Power
Rail
PCI_Vcc
Drive
PAR
Parity:
This pin generates PCI parity and ensures
even parity across AD[31:0] and C/BE[3:0]#.
During the address phase, PAR is valid after one
clock. With data phases, PAR is stable one clock
after a write or read transaction.
PCI Clock:
This input provides timing for all
transactions on the PCI bus to and from the
OZ6812. All PCI bus signals, except RST#, are
sampled and driven on the rising edge of
PCI_CLK. This input can be operated at
frequencies from 0 to 33 MHz.
Device Reset:
This input is used to initialize all
registers and internal logic to their reset states
and place most OZ6812 pins in a HIGH-
impedance state.
Grant
: This signal indicates that access to the bus
has been granted.
Request
: This signal indicates to the arbiter that
the OZ6812 requests use of the bus.
TTL
I/O
PCI
Spec
PCI_CLK
21
G4
-
I
PCI_Vcc
-
RST#
20
G2
-
I
AUX_Vcc
-
GNT#
2
B2
TTL
I
PCI_Vcc
PCI
Spec
PCI
Spec
REQ#
1
A1
-
TO
PCI_Vcc
Power Control and General Interface Pins
Pin Number
LQFP
59
Pin Name
Description
BGA
M8
Input
Type
Power
Rail
Aux_Vcc
Drive
RI_OUT/
PME#
Ring Indicate Out:
This pin is Ring Indicate
when the following occurs while O
Mode Control
B Register (index 2Eh) bit 7 is set to 1:
1)
Power Control (Index+02h) bit 7 set to 1
2)
Interrupt and General Control (Index+03h)
bit 7 set to 1
3)
PCI O2Micro Control 2 (Offset: D4h) bit X =
0
Power
Management
management event is the process by which the
OZ6812 can request a change of its power
consumption state. Usually, a PME occurs
during a request to change from a power saving
state to the fully operational state.
Speaker Output:
This output can be used to
support PC Card audio output. See O2 Mode E
Register (Index + 3Eh), bit 1.
Multifunction
Terminal
Multifunction MUX Register (Offset:08h).
Suspend:
This signal is used to protect the
internal registers from clearing when the PCI
RST# signal is asserted. When low, this signal is
used to mask the PCI RESET during suspend.
This pin can be used during suspend to prevent
controller reset.
Event:
A
power
-
TO
4mA
SPKR_OUT#
62
K8
TTL
I/O
Aux_Vcc
12mA
MF[6:0]
[6:0]:
See
PCI
69-67, 65-64,
61-60
70
L10, K9, N11,
L9, N10-9, L8
N12
TTL
I/O
Aux_Vcc
12mA
SUSPEND#
TTL
I
Aux_Vcc
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OZ6812B | ACPI CardBus Controller |
| OZ6812T | ACPI CardBus Controller |
| OZ6833 | ACPI CardBus Controller |
| OZ6833B | ACPI CardBus Controller |
| OZ6833T | ACPI CardBus Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OZ6812B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6812T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6833 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6833B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6833T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
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