參數(shù)資料
型號： OV8110
廠商： Electronic Theatre Controls, Inc.
英文描述： Advanced Information Preliminary
中文描述： 先進的信息初步
文件頁數(shù)： 2/28頁
文件大小： 180K
代理商： OV8110
Advanc ed Information
Preliminary
OV 8610/OV 8110
OV 8610 S INGLE-CHIP CMOS V GA COLOR DIGIT AL CAMERA
OV 8110 S INGLE-CHIP CMOS V GA B&W DIGIT AL CAMERA
Pin Description
Table 1. Pin Description
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A.
Tel: (408) 733-3030 Fax: (408) 733-3061
e-mail:
info@ovt.com
Website: http://www.ovt.com
Version 1.3, August 27, 2001
Page 2
Pin No.
01
02
Name
Pin Type
V
IN
Function
(Default=0)
Function
(Default=0)
Function/Description
SVDD
RESET
Array power (+3.3VDC). Bypass to ground with a 0.1
μ
F capacitor.
Chip reset, active high. Resets all control registers to factory defaults.
03
AGCEN
Automatic Gain Control (AGC) selection
“0” – Disable AGC
“1” – Enable AGC
Note: This function is disabled when OV8610/OV8110 sensor is configured in
SCCB low mode. In SCCB low mode this pin is an SCCB chip select function.
Frame exposure control
“0” – Disables frame exposure control
“1” – Enables frame exposure control
Array reference. Connect to ground with a 0.1
μ
F (min.) capacitor.
Analog substrate voltage
Analog ground
Analog power supply (+3.3VDC). Bypass to ground with a 0.1
μ
F capacitor.
Power-down mode selection.
“0” – Operating mode
“1” – Power-down mode
Charge pump out voltage. Doubler must be enabled.
Internal voltage reference. Bypass to ground with a 0.1
μ
F capacitor.
SCCB enable selection.
“0” – Selects internal register setting control and enables SCCB interface
“1” – Enables I/O input pin power on latch setting control
B&W CCIR analog composite signal output—for test purposes only
Analog power supply (+3.3VDC). Bypass to ground with a 0.1
μ
F capacitor.
Analog signal ground
Vertical sync output. At power-up, read as CSYS.
Field ID FODD output. At power-up, read as SRAM.
HREF output. At power-up, read as VSFRAM
Bit 7 of U video component output. At power-up, sampled as B8.
Bit 6 of U video component output. At power-up, sampled as TVEN.
Bit 5 of U video component output. At power-up, sampled as MIR.
Bit 4 of U video component output. At power-up, sampled as SLAEN.
Bit 3 of U video component output. At power-up, samples as ECLKO.
Bit 2 of U video component output. At power-up, sampled as QSVGA.
Bit 1 of U video component output. At power-up, sampled as CC656.
Bit 0 of U video component output. At power-up, sampled as GAMMA.
Crystal clock input
Crystal clock output
Digital power supply (+3.3VDC). Bypass to ground with a 0.1
μ
F capacitor.
Digital ground
Digital interface output buffer ground
Digital output buffer supply (+3.3VDC ). Bypass to ground with a 0.1
μ
F capacitor.
PCLK output. At power-up sampled as charge pump enable.
Bit 7 of Y video component output
Bit 6 of Y video component output
Bit 5 of Y video component output. At power-up, sampled as SHARP.
Bit 4 of Y video component output
04
FREX
Function
(Default=0)
05
06
07
08
09
VREQ
ASUB
AGND
AVDD
PWDN
V
REF
(1.5V)
V
IN
V
IN
V
IN
Function
(Default=0)
10
11
12
HVDD
V
C
CHG
SCCBB
V
REF
(5.0V)
V
REF
(2.7V)
Function
(Default=0)
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
VTO
ADVDD
ADGND
VSYNC/CSYS
FODD/SRAM
HREF/VSFRAM
*
UV7/B8
*
UV6/TVEN
*
UV5/MIR
*
UV4/SLAEN
*
UV3/ECLK0
*
UV2/QSVGA
*
UV1/CC656
*
UV0/GAMMA
XCLK1
XCLK2
DVDD
DGND
DOGND
DOVDD
PCLK/PWDB
Y7
Y6
Y5/SHARP
Y4
O
V
IN
V
IN
O
O
O
O
O
O
O
O
O
O
O
I
O
V
IN
V
IN
V
IN
V
IN
O
O
O
O
O
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