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參數(shù)資料
| 型號： | OV7910P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP CMOS COLOR PAL CAMERA |
| 中文描述： | 單芯片CMOS彩色PAL相機(jī) |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 247K |
| 代理商： | OV7910P |
OV7910P/OV7410P/OV7411P
12
Version 1.4
December 7, 1999
SINGLE IC CMOS COLOR & B/W PAL ANALOG CAMERAS
O
MNI
V
ISION
T
ECHNOLOGIES
, Inc.
Preliminary
below).
Figure 4. Bit Transfer on the I
2
C Bus
SDA
SCL
DATA
STABLE
DATA
CHANGE
ALLOWED
2.1
In I
2
C operation, the master must perform the following
operations:
I
2
C Bus Protocol Format
n
n
n
Generate the start/stop condition
Provide the serial clock on
SCL
Place the 7-bit slave address, the RW bit,
and the 8-bit subaddress on
SDA
The receiver must pull down SDA during the acknowl-
edge bit time. During the write cycle, the OV7910P/
OV7410P/OV7411P device returns the acknowledg-
ment and, during read cycle, the master returns the
acknowledgment except when the read data is the last
byte. If the read data is the last byte, the master does
not perform an acknowledge, indicating to the slave
that the read cycle can be terminated. Note that the
restart feature is not supported here.
Within each byte, MSB is always transferred first.
Read/write control bit is the LSB of the first byte. Stan-
dard I
2
C communications require only two pins: SCL
and SDA. SDA is configured as open drain for bidirec-
tional purpose. A HIGH to LOW transition on the SDA
while SCL is HIGH indicates a START condition. A
LOW to HIGH transition on the SDA while SCL is HIGH
indicates a STOP condition. Only a master can gener-
ate START/STOP conditions.
Except for these two special conditions, the protocol
that SDA remain stable during the HIGH period of the
clock, SCL. Each bit is allowed to change state only
when SCL is LOW (See Figure 4. Bit Transfer on the
I
2
C Bus and Figure 5. Data Transfer on the I
2
C Bus
I
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