
S INGLE IC CMOS  COLOR AND B/W DIGIT AL CAMERAS
during read cycle, the master returns acknowledge except the read 
data is the last byte. The master does not perform acknowledge if the 
read data is the last byte, indicates that the slave can terminate the 
read cycle. Note that the restart feature is not supported here.  
Within each byte, MSB is always transferred first. Read/write control 
bit is the LSB of the first byte. 
Standard I
2
C communications require only two pins: SCL and SDA. 
SDA is configured as open drain for bi-directional purpose. A HIGH 
to LOW transition on the SDA while SCL is HIGH indicates a 
START condition. A LOW to HIGH transition on the SDA while 
March 4, 2000 
Version 1.0 
20 
SCL is HIGH indicates a STOP condition. Only a master can generate 
START/STOP conditions.  
Except for these two special conditions, the protocol that SDA remain 
stable during the HIGH period of the clock, SCL. Each bit is allowed 
to change state only when SCL is LOW (See Figure * and Figure 10 
below). 
The OV6630/OV6130 I
2
C supports multi-byte write and multi-byte 
read. The master must supply the sub-address. in the write cycle, but 
not in the read cycle.  
DATA
STABLE
DATA CHANGE
ALLOWED
SDA
SCL
Figure 9. Bit Transfer on the I
2
C Bus 
SLAVD ID
SUB ADD
DATA
S
P
A
A
A
RW
SDA
SCL
Figure 10. Data Transfer on the I
2
C Bus 
Therefore, OV6630/OV6130 takes the read sub-address from the 
previous write cycle. In multi-byte write or multi-byte read cycles, the 
sub-address is automatically increment after the first data byte so that 
continuous locations can be accessed in one bus cycle. A multi-byte 
cycle overwrites its original sub-address; therefore, if a read cycle 
immediately follows a multi-byte cycle, you must insert a single byte 
write cycle that provides a new sub-address. 
OV6630/OV6130 can be power up pin programmed to one-of-eight 
slave ID addresses through function pins CS[2:0] (pins 35, 37, 34, 
respectively). 
Table 15. Slave ID Addresses 
CS[2:0] 
WRITE ID (hex) 
READ ID (hex) 
000 
C0 
C1 
001 
C4 
C5 
010 
C8 
C9 
011 
CC 
CD 
100 
D0 
D1 
101 
D4 
D5 
110 
D8 
D9 
111 
DC 
DD 
OV6630/OV6130 supports both single chip and multiple chip 
configurations. By asserting MULT (pin 47) to high, the sensor can be 
programmed for up to 8 slave ID addresses. Asserting MULT low 
configures OV6630/OV6130 for single ID slave address with address 
C0 for writes and address C1 for reads. MULT is internally defaulted 
to a low condition.