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參數(shù)資料
| 型號(hào)： | OV5116P |
| 英文描述： | B/W | PAL | 352 x 288 | ANALOG | CameraChip |
| 中文描述： | /黑白| PAL制式| 352 × 288 |模擬|的CameraChip |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | OV5116P |
OV5116P
May 4, 2001
Version 2.1
2
SINGLE IC CMOS MONOCHROME CAMERA WITH PAL ANALOG OUTPUT
O
MNI
V
ISION
T
ECHNOLOGIES
, Inc.
1.
This section describes the features and functions of the OV5116P, a monochrome CMOS video camera integrated circuit.
2.
Pin Assignments
:
Table 1.
Pin Descriptions
Introduction
* Pin 9 and Pin 24 must be used in a logical combination as per the following table:
Pin #
Name
Class
Function
1, 2, 20,
23, 26
AVDD, SVDD,
DVDD, OVDD
DEVDD
Bias
Power (+5V) connections.
3
VRCHG
OA
Internal voltage reference. Connect to AGND with a 0.1uF capacitor.
4
N50
I-
Set high(1)=PAL
5
ABOFF
I-
Auto brightness level descending function off
6
VCBRT
OA
Video DC Output Black level, leave it open in usual case
7, 21,
25, 28
SGND, DGND,
DEGND, AGND
Bias
Ground connections. Connect to supply common.
8
PAL
I-1
Set low()=CCIR/PAL mode.
*9
BKLT
I-
Backlight mode 1
10
XTAL2
XO
Oscillator clock output or crystal output.
11
XTAL1
XI
External oscillator input or crystal input; 13.5MHz
12
FSI
I-
External frame sync input. A rising edge on FSI sets the chip timing to vertical sync.
Leave open if unused.
13
OENB
I-
A logic level input to enable or tri-state CVO. Logic high(1)=tri-state;low()=enabled.
14
G4X
I-
A logic level input which when high places the maximum AGC gain to 4x. When low the
sensor AGC gain is 2x.
15
FAST
I-
A logic level input to enable/disable AGC/AEC FAST mode. High enables, low disables,
which provides slow and smooth AGC/AEC mode.
16
BPED
I-
A logic level input to disable on chip edge enhancement. High disable, low enable.
17
GAMMA
I-1
A logic level pin to select the transfer characteristic of output voltage versus light input.
Logic high for g=0.45; low for g=1.
18
FSO/MIRR
I/O
/
In/out pin.Frame Sync Output. Digital frame sync output pin. Positive pulse occurs during
the CVO vertical sync period. Input is a logic level input to enable mirror function.
Low()=Standard, High(1)=Mirror.
19
PCLK/G8X
I/O
/
Digital pixel clock output. Provides 2 functions: When high a valid pixel is present at CVO
and in sync with PCLK. Input is a logic level input to enable maximum AGC gain to 8x
(only effective when pin 14 is set to high(1))
22
CVO
Q
The composite video output signal. The output is a source follower capable of directly
driving a 1V p-p signal into a 108
load.(75
external and 33
internal)
*24
ATBLKT
I-
Backlight mode 2
27
VREQ
OA
Internal voltage reference level. Connect to AGND with a 0.1uF capacitor.
ATBLK(Pin 24)
1
1
BLKT(Pin 9)
1
1
Mode
Normal Mode
Mode 1 - Manual Back light
Mode 2 – Automatic Back light (Chip determination)
Future Use
Class
I-1
I-
I/O
OA
Q
XI/XO
Bias
Default Level
digital input, with 100k pull up
digital input, with 100k pull down
digital CMOS level input and output
analog CMOS reference voltage
75 ohm output
crystal input/output
power supply bias
: Low; O: Output
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