參數(shù)資料
型號: LM93CIMTX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: LJT 6C 6#12 PIN PLUG
中文描述: 16-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO56
封裝: MO-153EE, TSSOP-56
文件頁數(shù): 8/92頁
文件大小: 654K
代理商: LM93CIMTX
9.0 Pin Descriptions
Symbol
GPIO_0/TACH1
Pin #
1
Type
Digital I/O
(Open-Drain)
Digital I/O
(Open-Drain)
Digital I/O
(Open-Drain)
Digital I/O
(Open-Drain)
Digital I/O
(Open-Drain)
Digital I/O
(Open-Drain)
Digital I/O
(Open-Drain)
Digital I/O
(Open-Drain)
Digital Input
Digital Input
Digital Input
Function
Can be configured as fan tach input or a general purpose
open-drain digital I/O.
Can be configured as fan tach input or a general purpose
open-drain digital I/O.
Can be configured as fan tach input or a general purpose
open-drain digital I/O.
Can be configured as fan tach input or a general purpose
open-drain digital I/O..
A general purpose open-drain digital I/O. Can be configured to
monitor a CPU’s THERMTRIP signal to mask other errors.
A general purpose open-drain digital I/O. Can be configured to
monitor a CPU’s THERMTRIP signal to mask other errors.
Can be used to detect the state of CPU1 IERR or a general purpose
open-drain digital I/O
Can be used to detect the state of CPU2 IERR or a general purpose
open-drain digital I/O
CPU1 voltage regulator HOT
CPU2 voltage regulator HOT
SCSI Channel 1 termination fuse. Could also be used as a general
purpose input to trigger an error event.
SCSI Channel 2 termination fuse. Could also be used as a general
purpose input to trigger an error event.
Bidirectional System Management Bus Data. Output configured as
5V tolerant open-drain. SMBus 2.0 compliant.
System Management Bus Clock. Driven by an open-drain output,
and is 5V tolerant. SMBus 2.0 Compliant.
Open-drain ALERT output used in an interrupt driven system to
signal that an error event has occurred. Masked error events do not
activate the ALERT output. When in XOR tree test mode, functions
as XOR Tree output.
Open-drain reset output when power is first applied to the LM93.
Used as a reset for devices powered by 3.3V stand-by. After reset,
this pin becomes a reset input. See section 6.2 for more information.
Analog Ground
2.5V used for external ADC reference, or as a V
REF
reference
voltage
This is the negative input (current sink) from the CPU1 thermal
diode. Connected to THERMDC pin of Pentium processor or the
emitter of a diode connected MMBT3904 NPN transistor. Serves as
the negative input into the A/D for thermal diode voltage
measurements. A 100 pF capacitor is optional and can be
connected between REMOTE1 and REMOTE1+.
This is a positive connection to the CPU1 thermal diode. Serves as
the positive input into the A/D for thermal diode voltage
measurements. It also serves as a current source output that
forward biases the thermal diode. Connected to THERMDA pin of
Pentium processor or the base of a diode connected MMBT3904
NPN transistor. A 100 pF capacitor is optional and can be
connected between REMOTE1 and REMOTE1+.
GPIO_1/TACH2
2
GPIO_2/TACH3
3
GPIO_3/TACH4
4
GPIO_4 /
P1_THERMTRIP
GPIO_5 /
P2_THERMTRIP
GPIO_6
5
6
7
GPIO_7
8
VRD1_HOT
VRD2_HOT
SCSI_TERM1
9
10
11
SCSI_TERM2
12
Digital Input
SMBDAT
13
Digital I/O
(Open-Drain)
Digital Input
SMBCLK
14
ALERT/XtestOut
15
Digital Output
(Open-Drain)
RESET
16
Digital I/O
(Open-Drain)
AGND
V
REF
17
18
GROUND Input
Analog Output
REMOTE1
19
Remote Thermal
Diode_1- Input (CPU
1 THERMDC)
REMOTE1+
20
Remote Thermal
Diode_1+ I/O (CPU1
THERMDA)
L
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