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參數(shù)資料
| 型號： | ORT82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 1/109頁 |
| 文件大?。?/td> | 1379K |
| 代理商： | ORT82G51BM680-DB |
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Data Sheet
April, 2002
ORCA ORT82G5 1.0—1.25/2.0—2.5/3.125—3.5 Gbits/s
8b/10b SERDES Backplane Interface FPSC
Introduction
Lattice has developed a next generation FPSC
intended for high-speed serial backplane data trans-
mission. Built on the Series 4 recongurable embed-
ded system-on-chips (SoC) architecture, the
ORT82G5 is made up of backplane transceivers con-
taining eight channels, each operating at up to
3.5 Gbits/s (2.625 Gbits/s data rate), with a full-
duplex synchronous interface with built-in Rx clock
and data recovery (CDR), and Tx pre-emphasis
along with up to 400k usable FPGA system gates.
The CDR circuitry is a proven macrocell available
from Lattice's intellectual property library, and has
already been implemented in numerous applications,
including ASICs, standard products, and FPSCs, to
create interfaces for SONET/SDH, Fibre-channel,
Inniband, and Ethernet (GbE, 10 GbE) applica-
tions. With the addition of protocol and access logic
such as protocol-independent framers, asynchro-
nous transfer mode (ATM) framers, Fibre-channel or
Inniband link layer capabilities, packet-over-SONET
(POS) interfaces, and framers for HDLC for Internet
protocol (IP), designers can build a congurable
interface retaining proven backplane driver/receiver
technology. Designers can also use the device to
drive high-speed data transfer across buses within
any generic system. For example, designers can
build a 20 Gbits/s bridge for 10 Gbits/s Ethernet; the
high-speed SERDES interfaces can comprise two
XAUI interfaces with congurable back-end inter-
faces such as XGMII. The ORT82G5 can also be
used to provide a full 10 Gbits/s backplane data con-
nection with protection between a line card and
switch fabric.
The ORT82G5 offers a clockless high-speed inter-
face for interdevice communication on a board or
across a backplane. The built-in clock recovery of the
ORT82G5 allows for higher system performance,
easier-to-design clock domains in a multiboard sys-
tem, and fewer signals on the backplane. Network
designers will benet from the backplane transceiver
as a network termination device. The device supports
embedded 8b/10b encoding/decoding and link state
machines for 10G Ethernet, and bre-channel. The
ORT82G5 is also pinout compatible to the
ORSO82G5, which implements 8 channels of SER-
DES with SONET scrambling and cell processing.
Table 1. ORCA ORT82G5 Family—Available FPGA Logic
* The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate count
to a gate count assuming that 20% of the PFUs/SLICs are being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of
the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM
(EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the
embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calcula-
tions.
372 user I/Os out of a total of 432 user I/Os are bonded in the 680 PBGAM package.
Device
PFU
Rows
PFU
Columns
Total
PFUs
User I/O
LUTs
EBR
Blocks
EBR Bits
(k)
Usable*
Gates (k)
ORT82G5
36
1296
372/432
10,368
12
111
380—800
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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