參數(shù)資料
型號： OR4E04-1BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 1/153頁
文件大?。?/td> 2737K
代理商： OR4E04-1BM680I
Data Sheet
November, 2002
www.latticesemi.com
ORCA
Series 4 FPGAs
Introduction
Built on the Series 4 recon
fi
gurable embedded sys-
tem-on-a-chip (SoC) architecture, Lattice introduces
its new family of generic Field-Programmable Gate
Arrays (FPGAs). The high-performance and highly
versatile architecture brings a new dimension to
bringing network system designs to market in less
time than ever before. This new device family offers
many new features and architectural enhancements
not available in any earlier FPGA generations. Bring-
ing together highly
fl
exible SRAM-based programma-
ble logic, powerful system features, a rich hierarchy
of routing and interconnect resources, and meeting
multiple interface standards, the Series 4 FPGA
accommodates the most complex and high-perfor-
mance intellectual property (IP) network designs.
Programmable Features
■
High-performance platform design:
— 0.16 μm 7-level metal technology.
— Internal performance of >250 MHz.
— I/O performance of >420 MHz.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V
operation) translates to greater performance.
■
Traditional I/O selections:
— LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V)
I/Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-lim-
ited).
— Fast-capture input latch and input
fl
ip-
fl
op
(FF)/latch for reduced input setup time and zero
hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
■
New programmable high-speed I/O:
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, and IV), ZBT,
and DDR.
— Double-ended: LDVS, bused-LVDS, and
LVPECL. Programmable (on/off) internal parallel
termination (100
) also supported for these
I/Os.
Table 1.
ORCA
Series 4—Available FPGA Logic
* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following:
minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum
system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.
Note: Devices are not pinout compatible with
ORCA
Series 2/3.
Device
Rows
Columns
PFUs
User I/O
LUTs
EBR
Blocks
8
12
16
EBR Bits
(K)
74
111
148
Usable*
Gates (K)
201—397
333—643
471—899
OR4E02
OR4E04
OR4E06
26
36
46
24
36
44
624
1,296
2,024
405
466
466
4,992
10,368
16,192
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相關代理商/技術參數(shù)
參數(shù)描述
OR4E04-2BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04-2BA352I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04-2BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04-2BM416I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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