- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299576 > OR3T80-4PS208I FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 PDF資料下載
參數(shù)資料
| 型號(hào)： | OR3T80-4PS208I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁(yè)數(shù)： | 183/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T80-4PS208I |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)當(dāng)前第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)
74
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
Programmable Clock Manager (PCM):
Advance Information (continued)
Clock Multiplication
An output clock that is a multiple (not necessarily an
integer multiple) of the input clock can be generated in
PLL mode. The multiplication ratio is programmed in
the division registers DIV0, DIV1, and DIV2. Note that
DIV2 applies only to the ExpressCLK output of the
PCM
and any reference to DIV2 is implicitly 1 for the
system clock output of the PCM. The clock multiplica-
tion formulas when using ExpressCLK feedback are:
Where the values of DIV0, DIV1, and DIV2 range from
1 to 8.
The ExpressCLK multiplication range of output clock
frequencies is, therefore, from 1/8x up to 8x, with the
system clock range up to 8x the ExpressCLK frequency
or 64x the input clock frequency. If system clock feed-
back is used, the formulas are:
The divider values, DIV0, DIV1, and DIV2 are pro-
grammed in registers zero, one, and two, respectively.
The multiplied output is selected by setting register six,
bits [5:4] to 10 or 11 for ExpressCLK output and/or bits
[7:6] to 10 for system clock output. Note that when reg-
ister six, bits [5:4] are set to 11, the ExpressCLK output
is divided by DIV2, while the system clock cannot be
divided. The ExpressCLK divider is provided so that the
I/O clocking provided by the ExpressCLK can operate
slower than the internal system clock. This allows for
very fast internal processing while maintaining slower
interface speeds off-chip for improved noise and power
performance or to interoperate with slower devices in
the system.
It is also necessary to configure the internal PCM oscil-
lator for operation in the proper frequency range.
Table 29 shows the settings required for register four
for a given frequency range. The PCM oscillator fre-
quency range is chosen based on the desired output
frequency at the system clock output. If using the
ExpressCLK
output, the equivalent system clock fre-
quency can be selected by multiplying the expected
ExpressCLK
output frequency by the value for DIV2.
Choose the nominal frequency from the table that is
closest to the desired frequency, and use that value to
program register four. Minor adjustments to match the
exact input frequency are then performed automatically
by the PCM.
Note: Use of settings in the first three rows is not recommended.
X means “don’t care.”
FExpressCLK_OUT = FINPUT_CLOCK
DIV1
DIV0
FSYSTEM_CLOCK_OUT = FExpressCLK_OUT DIV2
FSYSTEM_CLOCK_OUT = FINPUT_CLOCK
DIV1
DIV0
FExpressCLK_OUT = FSYSTEM_CLOCK/DIV2
Table 29. PCM Oscillator Frequency Range
Register 4
7 6 5 4 3 2 1 0
Min
System
Clock
Output
Frequency
(MHz)
Nom
Max
0 0 X X X 0 0 0
12.80
102.40
192.00
0 0 X X X 0 0 1
12.54
81.52
150.50
0 0 X X X 0 1 0
12.28
79.85
147.41
0 0 X X X 0 1 1
12.03
78.17
144.31
0 0 X X X 1 0 0
11.77
76.49
141.21
0 0 X X X 1 0 1
11.51
74.81
138.12
0 0 X X X 1 1 0
11.25
73.14
135.02
0 0 X X X 1 1 1
10.99
71.46
131.92
0 1 X X X 0 0 0
10.74
69.78
128.83
0 1 X X X 0 0 1
10.48
68.10
125.73
0 1 X X X 0 1 0
10.22
66.43
122.63
0 1 X X X 0 1 1
9.96
64.75
119.54
0 1 X X X 1 0 0
9.70
63.07
116.44
0 1 X X X 1 0 1
9.45
61.39
113.34
0 1 X X X 1 1 0
9.19
59.72
110.25
0 1 X X X 1 1 1
8.93
58.04
107.15
1 0 0 0 0 X X X
8.67
56.36
104.05
1 0 0 0 1 X X X
8.41
54.68
100.95
1 0 0 1 0 X X X
8.15
53.01
97.86
1 0 0 1 1 X X X
7.90
51.33
94.76
1 0 1 0 0 X X X
7.64
49.65
91.66
1 0 1 0 1 X X X
7.38
47.97
88.57
1 0 1 1 0 X X X
7.12
46.30
85.47
1 0 1 1 1 X X X
6.86
44.62
82.37
1 1 0 0 0 X X X
6.61
42.94
79.28
1 1 0 0 1 X X X
6.35
41.26
76.18
1 1 0 1 0 X X X
6.09
39.59
73.08
1 1 0 1 1 X X X
5.83
37.91
69.99
1 1 1 0 0 X X X
5.57
36.23
66.89
1 1 1 0 1 X X X
5.32
34.55
63.79
1 1 1 1 0 X X X
5.06
32.88
60.70
1 1 1 1 1 X X X
4.80
31.20
57.60
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T80-4PS208 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PQFP208 |
| OR3T125-4PS240I | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP240 |
| OR3T125-4PS240 | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP240 |
| OR3T55-4PS240I | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP240 |
| OR3T55-4PS240 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T80-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T80-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T80-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T80-5BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。