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| 型號(hào)： | OR3T55-4BA256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 134/210頁(yè) |
| 文件大小： | 2138K |
| 代理商： | OR3T55-4BA256 |
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Lucent Technologies Inc.
3
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the
ORCA Series 3 include:
T Full PCI local bus compliance.
T New dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to
i960 * and
PowerPC processors with user-configurable
address space provided.
T New parallel readback of configuration data capabil-
ity with the built-in microprocessor interface.
T New programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates from
5 MHz to 80 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
T True, internal, 3-state, bidirectional buses with sim-
ple control provided by the new SLIC.
T 32 x 4 RAM per PFU, configurable as single- or dual-
port at >125 MHz. Create large, fast RAM/ROM
blocks (128 x 8 in only eight PFUs) using the new
SLIC decoders as bank drivers.
*
i960 is a registered trademark of Intel Corporation.
PowerPC is a registered trademark of International Business
Machines Corporation.
Table 2.
ORCA Series 3 System Performance
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
Note: Shaded values are advance information and are valid for OR3Txxx devices only.
Parameter
# PFUs
Speed
Unit
-4
-5
-6
16-bit Loadable Up/Down Counter
2
68
90
121
MHz
16-bit Accumulator
2
68
90
121
MHz
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1
ROM Mode, Unpipelined2
Multiplier Mode, Pipelined3
11.5
8
15
23
58
85
31
76
119
41
104
163
MHz
32 x 16 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
4
128
157
174
209
235
283
MHz
128 x 8 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
8
113
153
208
MHz
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs6
0.25
0
4.87
2.35
3.66
1.82
2.69
1.36
ns
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs7
2
0
15.05
5.90
11.20
4.53
8.01
3.41
ns
36-bit Parity Check (internal)
2
15.05
11.20
8.01
ns
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PDF描述 |
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| OR3T55-4BA352 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA352 |
| OR3T80-4BA352I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T55-4BA256I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-4PS208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-5BA256 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-5BA256I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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