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參數(shù)資料
| 型號： | OR3T165-6B600 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1024 CLBS, 120000 GATES, PBGA600 |
| 封裝： | BGA-600 |
| 文件頁數(shù)： | 157/210頁 |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T165-6B600 |
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50
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
Clock Distribution Network (continued)
ExpressCLK Inputs
There are four dedicated ExpressCLK pads on each
Series 3 device: one in the middle of each side. Two
other user I/O pads can also be used as corner
ExpressCLK
inputs, one on the lower-left corner, and
one on the upper-right corner. The corner ExpressCLK
pads feed the ExpressCLK to the two sides of the array
that are adjacent to that corner, always driving the
same signal in both directions. The ExpressCLK route
from the middle pad and from the corner pad associ-
ated with that side are multiplexed and can be glitch-
lessly stopped/started under user control using the
StopCLK
feature of the CLKCNTRL function block
(described under Special Function Blocks) on that side.
The ExpressCLK output of the programmable clock
manager (PCM) is programmably connected to the cor-
ner ExpressCLK routes. PCM blocks are found in the
same corners as the corner ExpressCLK signals and
are described in the Special Function Blocks section.
The ExpressCLK structure is shown in Figure 34 (PCM
blocks are not shown).
Note: All multiplexers are set during configuration.
Figure 34. ExpressCLK and Fast Clock Distribution
Selecting Clock Input Pins
Any user I/O pin on an
ORCA FPGA can be used as a
fast, low-skew system clock input. Since the four dedi-
cated ExpressCLK inputs can only be used to distribute
global signals into the FPGA, these pins should be
selected first as clock pins. Within the interquad region
of the device, these clocks sourced by the ExpressCLK
inputs are called Fast Clocks. Choosing the next clock
pin is completely arbitrary, but using a pin that is near
the center of an edge of the device will provide the low-
est skew system clock network. The pin-to-pin timing
numbers in the Timing Characteristics section assume
that the clock pin is in one of the PICs at the center of
any side of the device next to an ExpressCLK pad. For
actual timing characteristics for a given clock pin, use
the timing analyzer results from
ORCA Foundry.
To select subsequent clock pins, certain rules should
be followed. As discussed in the Programmable Input/
Output Cells section, PICs are grouped into adjacent
pairs. Each of these pairs contains eight I/Os, but only
one of the eight I/Os in a PIC pair can be routed directly
onto a system clock spine. Therefore, to achieve top
performance, the next clock input chosen should not be
one of the pins from a PIC pair previously used for a
clock input. If it is necessary to have a second input in
the same PIC pair route onto global system clock rout-
ing, the input can be routed to a free clock spine using
the PIC switching segment (pSW) connections to the
clock spine network at some small sacrifice in speed.
Alternatively, if global distribution of the secondary
clock is not required, the signal can be routed on long
lines (xL) and input to the PFU clock input without
using a clock spine.
Another rule for choosing clock pins has to do with the
alternating nature of clock spine connections to the xL
and pxL routing segments. Starting at the left side of
the device, the first vertical clock spine from the top
connects to hxL[0] (horizontal xL[0]), and the first verti-
cal clock spine from the bottom connects to hxL[5] in all
PLC rows. The next vertical clock spine from the top
connects to hxL[1], and the next one from the bottom
connects to hxL[6]. This progression continues across
the device, and after a spine connects to hxL[9], the
next spine connects to hxL[0] again. Similar connec-
tions are made from horizontal clock spines to vxL (ver-
tical xL) lines from the top to the bottom of the device.
Because the
ORCA Series 3 clock routing only
requires the use of an xL line in every other row or col-
umn, even two inputs chosen 20 PLCs apart on the
same xL line will not conflict, but it is always better to
avoid these choices, if possible. The Fast Clock spines
in the interquad routing region also connect to xL[8]
and xL[9] for each set of xL lines, so it is better to avoid
user I/Os that connect to xL[8] or xL[9] when a Fast
Clock is used that might share one of these connec-
tions. Another reason to use the Fast Clock spines is
that since they use only the xL[9:8] lines, they will not
conflict with internal data buses which typically use
xL[7:0]. For more details on clock selection, refer to
application notes on clock distribution in
ORCA Series
3 devices.
ExpressCLKs TO PIOs
FAST CLOCKS
ExpressCLK PADS
CLKCNTRL
BLOCK
5-5802(F)
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| OR3T165-6BA352I | FPGA, 1024 CLBS, 120000 GATES, PBGA352 |
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| OR3T165-6BC432I | FPGA, 1024 CLBS, 120000 GATES, PBGA432 |
| OR3T165-6BC600I | FPGA, 1024 CLBS, 120000 GATES, PBGA600 |
| OR3T165-6PS208I | FPGA, 1024 CLBS, 120000 GATES, PQFP208 |
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