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| 型號(hào)： | OR3T1256PS240-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP2-240 |
| 文件頁(yè)數(shù)： | 153/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T1256PS240-DB |
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Lattice Semiconductor
53
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Special Function Blocks (continued)
The readback frame contains the conguration data
and the state of the internal logic. During readback, the
value of all registered PFU and PIC outputs can be
captured. The following options are allowed when
doing a capture of the PFU outputs.
1. Do not capture data (the data written to the RAMs,
usually 0, will be read back).
2. Capture data upon entering readback.
3. Capture data based upon a congurable signal
internal to the FPGA. If this signal is tied to
logic 0, capture RAMs are written continuously.
4. Capture data on either options 2 or 3 above.
The readback frame has an identical format to that of
the conguration data frame, which is discussed later
in the Conguration Data Format section. If LUT mem-
ory is not used as RAM and there is no data capture,
the readback data (not just the format) will be identical
to the conguration data for the same frame. This
eases a bitwise comparison between the conguration
and readback data. The conguration header, including
the length count eld, is not part of the readback frame.
The readback frame contains bits in locations not used
in the conguration. These locations need to be
masked out when comparing the conguration and
readback frames. The development system optionally
provides a readback bit stream to compare to readback
data from the FPGA. Also note that if any of the LUTs
are used as RAM and new data is written to them,
these bits will not have the same values as the original
conguration data frame either.
Global 3-State Control (TS_ALL)
To increase the testability of the
ORCA Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
conguration, the TS_ALL signal is driven by the input
pad RD_CFG. After conguration, the TS_ALL signal
can be disabled, driven from the RD_CFG input pad, or
driven by a general routing signal in the upper right cor-
ner. Before conguration, TS_ALL is active-low; after
conguration, the sense of TS_ALL can be inverted.
The following occur when TS_ALL is activated:
1. All of the user I/O output buffers are 3-stated, the
user I/O input buffers are pulled up (with the pull-
down disabled), and the input buffers are congured
with TTL input thresholds (OR3Cxx only).
2. The TDO/RD_DATA output buffer is 3-stated.
3. The RD_CFG, RESET, and PRGM input buffers remain
active with a pull-up.
4. The DONE output buffer is 3-stated, and the input
buffer is pulled up.
Internal Oscillator
The internal oscillator resides in the lower left corner of
the FPGA array. It has output clock frequencies of
1.25 MHz and 10 MHz. The internal oscillator is the
source of the internal CCLK used for conguration. It
may also be used after conguration as a general-
purpose clock signal.
Global Set/Reset (GSRN)
The GSRN logic resides in the lower right corner of the
FPGA. GSRN is an invertible, default, active-low signal
that is used to reset all of the user-accessible latches/
FFs on the device. GSRN is automatically asserted at
powerup and during conguration of the device.
The timing of the release of GSRN at the end of cong-
uration can be programmed in the start-up logic
described below. Following conguration, GSRN may
be connected to the RESET pin via dedicated routing, or
it may be connected to any signal via normal routing.
Within each PFU and PIO, individual FFs and latches
can be programmed to either be set or reset when
GSRN is asserted. A new option in Series 3 allows
individual PFUs and PIOs to turn off the GSRN signal
to its latches/FFs after conguration.
The RESET input pad has a special relationship to
GSRN. During conguration, the RESET input pad
always initiates a conguration abort, as described in
the FPGA States of Operation section. After congura-
tion, the global set/reset signal (GSRN) can either be
disabled (the default), directly connected to the RESET
input pad, or sourced by a lower-right corner signal. If
the RESET input pad is not used as a global reset after
conguration, this pad can be used as a normal input
pad.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T1256PS240I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1257PS208-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T306S240I-DB | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
| OR3T307S240-DB | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
| OR3T556PS240-DB | FPGA, 324 CLBS, 80000 GATES, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-6PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256PS240I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-7BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1257BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-7BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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