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參數(shù)資料
| 型號(hào)： | OR3T125-4PS240 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP240 |
| 封裝： | SQFP-240 |
| 文件頁數(shù)： | 190/210頁 |
| 文件大小： | 2138K |
| 代理商： | OR3T125-4PS240 |
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80
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
Programmable Clock Manager (PCM):
Advance Information (continued)
High-Speed Internal Processing with Slow I/Os
The PCM PLL mode provides two outputs, one sent to
the global system clock routing of the FPGA and the
other to the ExpressCLK(s) that serve the FPGA I/Os.
The ExpressCLK output of the PCM has a divide capa-
bility (DIV2) that the system clock output does not. This
feature allows an input clock to be multiplied up to a
higher frequency for high-speed internal processing,
and also allows the ExpressCLK output to be divided
down to a lower frequency to accommodate off-FPGA
data transfers. For example, a 10 MHz input clock may
be multiplied (see Clock Multiplication in the Phase-
Locked Loop (PLL) Mode subsection) to 25 MHz (DIV0
= 4, DIV1 = 5, DIV2 = 2) and output to the FPGA
ExpressCLK
. This allows the
I/Os of the circuit to run at 25 MHz ((2 * 5)/4 * 10 MHz).
The system clock will run at DIV2 times the Express-
CLK
rate, which is 2 times 25 MHz, or 50 MHz. This
setup allows for internal processing to occur at twice
the rate of on/off device I/O transfers.
PCM Cautions
Cautions do apply when using the PCM. There are a
number of configurations that are possible in the PCM
that are theoretically valid, but may not produce viable
results. This section describes some of those situa-
tions, and should leave the user with an understanding
of the types of pitfalls that must be avoided when modi-
fying clock signals.
Resultant signals from the PCM must meet the FPGA
timing specifications. It is possible to specify pulses by
using duty-cycle adjustments that are too narrow to
function in the FPGA. For instance, if a 40 MHz clock is
doubled to 80 MHz and a 6.25% duty cycle is selected,
the result will be a 780 ps pulse that repeats every
12.5 ns. This pulse falls outside of the clock pulse width
specification and is not valid.
Using divider DIV2, it is possible to specify a clock mul-
tiplication factor of 64 between the input clock and the
output system clock. As mentioned above, the result-
ant frequency must meet all FPGA timing specifica-
tions. The input clock must also meet the minimum
specifications. An input clock rate that is below the
PCM
clock minimum cannot be used even if the multi-
plied output is within the allowable range.
The use of the PCM to tweak a clock signal to eliminate
a particular problem, such as a single setup time viola-
tion, is discouraged. A small shift in delay, duty cycle,
or phase to correct a single-point problem is in essence
an asynchronous patch to a synchronous system, mak-
ing the system less stable. This type of local problem,
as opposed to a global clock control issue like device-
wide clock delay, can usually be eliminated through
more robust design practices. If this type of change is
made, the designer must be aware that depending on
the extent of the change made, the design may fail to
operate correctly in a different speed grade or voltage
grade (e.g., 3C vs. 3T), or even in a different produc-
tion lot of the same device.
Divider DIV2 is available in DLL mode for the Express-
CLK
output, but its use is not recommended with duty-
cycle adjusted clocks.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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| OR3T125-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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