參數(shù)資料
型號： OR2T15B
廠商： Lattice Semiconductor Corporation
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場可編程門陣列
文件頁數(shù)： 67/192頁
文件大?。?/td> 935K
代理商： OR2T15B
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Data Sheet
January 2002
ORCA
Series 2 FPGAs
Lattice Semiconductor
67
Special-Purpose Pins
Special-Purpose Pins (Become User I/O After Configuration)
(continued)
M0, M1, M2
I
During powerup and initialization, M0—M2 are used to select the con
fi
guration mode
with their values latched on the rising edge of INIT. See Table 7 for the con guration
modes. During con
fi
guration, a pull-up is enabled, and after con
fi
guration, the pins are
user-programmable I/O*.
M3
I
During powerup and initialization, M3 is used to select the speed of the internal oscilla-
tor during con
fi
guration, with its value latched on the rising edge of INIT. When M3 is
low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz.
During con
fi
guration, a pull-up is enabled, and after con
fi
guration, this pin is a user-pro-
grammable I/O pin*.
TDI, TCK, TMS
I
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs. If boundary scan is not selected, all boundary-scan functions are inhibited once
con
fi
guration is complete, and these pins are user-programmable I/O pins. Even if
boundary scan is not used, either TCK or TMS must be held at logic 1 during con gura-
tion. Each pin has a pull-up enabled during con
fi
guration*.
HDC
O
High During Con
fi
guration is output high until con
fi
guration is complete. It is used as a
control output indicating that con
fi
guration is not complete. After con
fi
guration, this pin
is a user-programmable I/O pin*.
LDC
O
Low During Con
fi
guration is output low until con
fi
guration is complete. It is used as a
control output indicating that con
fi
guration is not complete. After con
fi
guration, this pin
is a user-programmable I/O pin*.
INIT
I/O
INIT is a bidirectional signal before and during con
fi
guration. During con guration, a
pull-up is enabled, but an external pull-up resistor is recommended. As an active-low
open-drain output, INIT is held low during power stabilization and internal clearing of
memory. As an active-low input, INIT holds the FPGA in the wait-state before the start
of con
fi
guration. After con
fi
guration, the pin is a user-programmable I/O pin*.
CS0, CS1, WR, RD
I
CS0, CS1, WR, RD are used in the asynchronous peripheral con
fi
guration modes. The
FPGA is selected when CS0 is low and CS1 is high. When selected, a low on the write
strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR
CS1 are also used as chip selects in the slave parallel mode.
, and
A low on RD changes D7 into a status output. As a status indication, a high indicates
ready and a low indicates busy. WR and RD should not be used simultaneously. If they
are, the write strobe overrides. During con
fi
guration, a pull-up is enabled, and after con-
fi
guration, the pins are user-programmable I/O pins*.
During master parallel con
fi
guration mode, A[17:0] address the con
fi
guration EPROM.
During con
fi
guration, a pull-up is enabled, and after con
fi
guration, the pins are user-
programmable I/O pins*.
During master parallel, peripheral, and slave parallel con
fi
guration modes, D[7:0]
receive con
fi
guration data and each pin has a pull-up enabled. After con guration, the
pins are user-programmable I/O pins*.
During con
fi
guration, DOUT is the serial data output that can drive the DIN of daisy-
chained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
After con
fi
guration, DOUT is a user-programmable I/O pin*.
A[17:0]
O
D[7:0]
I
DOUT
O
Table 17. Pin Descriptions
(continued)
Symbol
I/O
Description
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con
fi
guration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
Pin Information
(continued)
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參數(shù)描述
OR2T15B7A352-DB 制造商:Rochester Electronics LLC 功能描述:- Bulk
OR2T15B7BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T15B7BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 1600 LUT 307 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T15B7BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T15B7BA352I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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