- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383721 > OR2T04A-6M208 (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | OR2T04A-6M208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 39/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T04A-6M208 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁
Lucent Technologies Inc.
39
Data Sheet
June 1999
ORCA Series 2 FPGAs
Clock Distribution Network
(continued)
Alternatively, the clock can be routed from the spine to
the branches by using the BIDIs instead of the long-line
drivers. This results in added delay in the clock net, but
the clock skew is approximately equal to the clock
routed using the long-line drivers. This method can be
used to create a clock that is used in only one quad-
rant. The XH lines act as a clock spine, which is then
routed to perpendicular XH lines (the branches) using
the BIDIHs.
Clock signals, such as the output of a counter, can also
be generated in PLCs and routed onto an XL line,
which then acts as a clock spine. Although the clock
can be generated in any PLC, it is recommended that
the clock be located as close to the center of the FPGA
as possible to minimize clock skew.
Selecting Clock Input Pins
Any user I/O pin on an ORCA FPGA can be used as a
very fast, low-skew clock input. Choosing the first clock
pin is completely arbitrary, but using a pin that is near
the center of an edge of the device (as shown in Fig-
ures 34 and 35) will provide the lowest skew clock net-
work. The pin-to-pin timing numbers in the Timing
Characteristics section of this data book assume that
the clock pin is in one of the four PICs at the center of
any side of the device.
Once the first clock pin has been chosen, there are
only two sets of pins (within the center four PICs on
each side of the device) that should not be chosen as
the second clock pin: a pin from the same PIC, and/or a
pin from the PIC on the exact opposite edge of the die
(i.e., if a pin from a PIC on the top edge is chosen for
the first clock, the same PIC on the bottom edge should
not be chosen for the second clock).
These rules should be followed iteratively until a total of
eight clocks (or other global signals) have been
selected: four from the left/right sides of the device, and
four from the top/bottom sides of the device. If more
than eight clocks are needed, then select another pin
outside the center four PICs to use primary-clock rout-
ing, use secondary clock routing for any pin, or use
local clock routing.
If it is desired to use a pin for one of the first eight
clocks that is not within the center four PICs of any side
of the device and primary clock routing is desired, the
pad names (see Pin Information) of the two clock pins
on the top or bottom of the device
cannot
be a multi-
plier of four PICs away. The same rule applies to clock
pins on the left or right side of the device.
The following equation can be used to determine pin
names:
Pad number = P[RL][TB]n ± (i x 4)[A – D]
Where i = 1—8, and n is the current PIC number.
For more information, please refer to Utilizing the
ORCA
OR2C/TxxA Clock Distribution Network Appli-
cation Note (AP97-055FPGA).
SEE DETAIL A
CLK PIN
5-4481(F).r2
Figure 35. Secondary Clock Distribution
DT
DT
DT
DT
CLOCK
BRANCHES
CLOCK SPINE
SEE DETAIL B
PFU
HCK
VCK
DETAIL B
PA
PB
V
DETAIL A
V
V
V
V
V
V
V
PC
PD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2T04A-6M208I | Field-Programmable Gate Arrays |
| OR2T04A-6M84 | Field-Programmable Gate Arrays |
| OR2T04A-6M84I | Field-Programmable Gate Arrays |
| OR2T04A-6PS208 | Field-Programmable Gate Arrays |
| OR2T04A-6PS208I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T04A-6M208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6M84 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6M84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6PS100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6PS100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。